Testable integrated circuit and test method therefor
View Patent ↗Disclosed is an integrated circuit ( 200 ) comprising a plurality of cores ( 110, 110 ), at least some of the cores being located in different power domains (VDD 1 , VDD 2 ), each core being surrounded by a test wrapper ( 220 ) comprising a plurality of wrapper cells ( 128, 230 ), wherein each of said test wrappers are located in a single power domain (VDD 3 ) and each plurality of wrapper cells comprises wrapper output cells ( 230 ) each arranged to output a signal from its associated core, each of said wrapper output cells comprising an output level shifter ( 232, 240 ) for shifting the voltage of said signal to the voltage of the single power domain (VDD 3 ). A method for testing such an IC and standard library cells for designing such an IC are also disclosed.
1. An integrated circuit comprising a plurality of cores, at least some of the cores being located in different power domains, each core being surrounded by a test wrapper comprising a plurality of wrapper cells, wherein each of said test wrappers are located in a single power domain and each plurality of wrapper cells comprises wrapper output cells each arranged to output a signal from its associated core, each of said wrapper output cells comprising an output level shifter for shifting the voltage of said signal to the voltage of the single power domain.
2. The integrated circuit of claim 1 , wherein each plurality of wrapper cells further comprises wrapper input cells each arranged to provide a signal to its associated core, each wrapper input cell comprising an input level shifter for shifting the voltage of the single power domain to the voltage of the power domain of its associated core.
3. The integrated circuit of claim 1 , wherein each wrapper output cell comprises:
a primary input, a test input, a primary output and a test output; and
a multiplexer responsive to an input selection signal for coupling a selected one of the primary input and the test input to the primary output, the level shifter being coupled between the primary input and the primary output.
4. The integrated circuit of claim 3 , wherein the multiplexer comprises the level shifter.
5. The integrated circuit of claim 4 , wherein the multiplexer comprises a first input, a second input, an output and a control terminal for receiving the input selection signal for selecting one of the first input and the second input;
a selection stage comprising a plurality of series-connected transistors between the supply line of the single power domain and ground including a first transistor connected between said supply line and a first node, at least one of said series-connected transistors being responsive to the first input and at least one of said series-connected transistors being responsive to the selection signal;
a level shifter stage comprising a first further transistor coupled between the said supply line and a second node and a second further transistor coupled between the second node and the first input, the first further transistor having its control terminal coupled to the first node, the second further transistor having its control terminal coupled to a supply line of the power domain of its associated core and the first transistor having its control terminal coupled to the first further node.
6. The integrated circuit of claim 3 , wherein at least some wrapper output cells further comprise a further multiplexer responsive to a further input selection signal for coupling a selected one of the test input and the primary output to the test output.
7. The integrated circuit of claim 6 , wherein the further multiplexer comprises a further output level shifter for shifting the voltage of said signal to the voltage of the single power domain.
8. The integrated circuit of claim 3 , wherein at least some of the wrapper output cells further comprise a data storage element between the test input and the multiplexer for providing another wrapper output cell with a fixed logic value during test.
9. An electronic device comprising the integrated circuit of claim 1 , the electronic device comprising a plurality of power supplies for powering the respective power domains of the integrated circuit.
10. A multiplexer for use in an integrated circuit of claim 1 , the multiplexer comprising a first input, a second input, an output and a control terminal for receiving the input selection signal for selecting one of the first input and the second input;
a selection stage comprising a plurality of series-connected transistors between a first supply line and ground including a first transistor connected between said supply line and a first node, at least one of said series-connected transistors being responsive to the first input and at least one of said series-connected transistors being responsive to the selection signal;
a level shifter stage comprising a first further transistor coupled between the said supply line and a second node and a second further transistor coupled between the second node and the first input, the first further transistor having its control terminal coupled to the first node, the second further transistor having its control terminal coupled to a further supply line and the first transistor having its control terminal coupled to the first further node.
11. A non-transitory computer-readable medium comprising a library of standard cells for designing an integrated circuit, said library comprising a standard cell including the multiplexer of claim 10 .
12. The non-transitory computer-readable medium of claim 11 , wherein the standard cell comprises a wrapper cell including said multiplexer.
13. The non-transitory computer-readable medium of claim 12 , wherein the wrapper cell comprises a primary input, a test input, a primary output and a test output; and wherein the multiplexer has a control input for receiving an input selection signal for coupling a selected one of the primary input and the test input to the primary output.
14. The non-transitory computer readable medium of claim 11 , further comprising a program for designing an integrated circuit, said program being arranged to, when executed on a computer, produce a technology-specific representation of the integrated circuit by selecting standard cells from said library in response to an abstract specification of the integrated circuit.
15. A method of testing an integrated circuit according to claim 1 , comprising:
selecting one of the cores for testing;
bringing the wrapper of the selected core in a test mode,
providing the core with a test stimulus via said wrapper,
capturing the response of the core to the test stimulus;
shifting, in an wrapper output cell, the voltage level of the response to the voltage of the single power domain; and
communicating the test response to an output of the integrated circuit.