Semiconductor memory device and a method of manufacturing the same, a method of manufacturing a vertical MISFET and a vertical MISFET, and a method of manufacturing a semiconductor device and a semiconductor device
View Patent ↗Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.
1. A method of manufacturing a semiconductor device including memory cells including MISFETs, comprising steps of:
(a) forming a first film over a conductive film formed over a main surface of a semiconductor substrate;
(b) patterning a first film along a first direction by using a first resist film as a mask;
(c) after the step (b), removing the first resist film;
(d) after the step (c), patterning the first film along a second direction substantially perpendicular to the first direction by using a second resist film as a mask; and
(e) after the step (d), removing the second resist film;
(f) after the step (e), patterning the conductive film by using the first film patterned in the step (e) to form gate patterns for gate electrodes of the MISFETs,
wherein the memory cell comprises a memory cell of a static random memory, wherein the memory cell includes a first drive MISFET, a second drive MISFET, a first transfer MISFET and a second transfer MISFET such that the first drive MISFET and the first transfer MISFET are cross-coupled to the second drive MISFET and the second transfer MISFET, and
wherein the first drive MISFET and the first transfer MISFET are arranged with point symmetry to the second drive MISFET and the second transfer MISFET, respectively, with respect to a center point in a memory cell forming region.
2. A method according to claim 1 , wherein the gate patterns are formed such that a gate electrode of the first drive MISFET is integrally formed with a gate electrode of the first transfer MISFET and such that a gate electrode of the second drive MISFET is integrally formed with a gate electrode of the second transfer MISFET.
3. A method according to claim 1 ,
wherein a gate pattern of the first film for a gate electrode of an MISFET in a peripheral circuit is formed by using the step (b) or the step (d).
4. A method according to claim 1 , wherein a gate pattern of the first film for a gate electrode of an MISFET in a peripheral circuit is formed by using the step (b), the step (b) and the step (f).
5. A method according to claim 1 , wherein the first film includes a silicon oxide film.
6. A method according to claim 1 , wherein the memory cells arranged in the first direction are arranged with the same layout pattern in the first direction.
7. A method according to claim 1 ,
wherein the step (f) is performed without using any resist films.