Integrated circuit with power state determination circuit
An integrated circuit in which a power terminal, a ground terminal, an input terminal and an internal circuit are formed, has a unidirectional circuit of a direction from the input terminal to the power terminal, the unidirectional circuit being provided between the input terminal and the power terminal; and a power state determination circuit which detects whether the power terminal is connected to an external power source or not to output a power open detection signal. And the unidirectional circuit includes a first transistor in which a voltage of the power terminal is applied to a gate, and a second transistor connected to the first transistor in series, and a voltage of the external power source is input to the input terminal.
1. An integrated circuit in which a power terminal, a ground terminal, an input terminal and an internal circuit are formed, comprising:
a unidirectional circuit of a direction from the input terminal to the power terminal, the unidirectional circuit being provided between the input terminal and the power terminal, the unidirectional circuit including a first transistor and a second transistor, a voltage of the power terminal being applied to a gate of the first transistor, the first transistor and the second transistor being connected in series between the input terminal and the power terminal; and
a power state determination circuit which detects whether the power terminal is connected to an external power source or not to output a power open detection signal,
wherein a voltage of the external power source is input to the input terminal.
2. The integrated circuit according to claim 1 ,
wherein the power state determination circuit includes:
a first voltage-dividing circuit which divides a voltage between the input terminal and the ground terminal to generate a first voltage-dividing signal;
a second voltage-dividing circuit which divides a voltage between the power terminal and the ground terminal to generate a second voltage-dividing signal; and
a comparator which compares the first and second voltage-dividing signals to output the power open detection signal.
3. The integrated circuit according to claim 1 ,
wherein the power state determination circuit operates as a power supply voltage detection circuit having a function of detecting a voltage of the power terminal, and detects whether the voltage of the power terminal is lower than a reference voltage and outputs the power open detection signal.
4. The integrated circuit according to claim 1 ,
wherein the first and second transistors are P-channel MOS transistors, and
wherein the second transistor is provided between the first transistor and the power terminal, and a gate is connected to a drain terminal of the first transistor.
5. The integrated circuit according to claim 1 ,
wherein the first and second transistors are P-channel MOS transistors, and
wherein the second transistor is provided between the first transistor and the input terminal, and a gate is connected to a source terminal of the first transistor.
6. The integrated circuit according to claim 1 ,
wherein the first and second transistors are P-channel MOS transistors, and
wherein the second transistor is provided between the first transistor and the input terminal, and a gate is connected to a gate of the first transistor.
7. The integrated circuit according to claim 1 ,
wherein the first and second transistors are P-channel MOS transistors provided to different N-type well regions respectively, and
wherein the second transistor is provided between the first transistor and the input terminal, and a gate is connected to a source terminal of the first transistor.
8. The integrated circuit according to claim 1 ,
wherein the first and second transistors are P-channel MOS transistors provided to different N-type well regions respectively, and
wherein the second transistor is provided between the first transistor and the power terminal, and a gate is connected to a drain terminal of the first transistor.
9. An integrated circuit in which a power terminal, a ground terminal, an input terminal and an internal circuit are formed, comprising:
a unidirectional circuit of a direction from the ground terminal to the input terminal, the unidirectional circuit being provided between the input terminal and the ground terminal, the unidirectional circuit including a first transistor and a second transistor, a voltage of the ground terminal being applied to a gate of the first transistor, the first transistor and the second transistor being connected in series between the input terminal and the ground terminal; and
a power state determination circuit which detects whether the ground terminal is connected to an external ground terminal or not to output a ground open detection signal,
wherein a voltage of the external ground terminal is input to the input terminal.
10. The integrated circuit according to claim 9 ,
wherein the power state determination circuit includes:
a third transistor in which the input terminal is connected to a gate and in which a source and a drain are connected between the power terminal and the ground terminal;
a fourth transistor in which the ground terminal is connected to a gate and in which a source and a drain are connected between the power terminal and the ground terminal; and
a comparator which compares potentials of nodes between the drains of the third and fourth transistors and the power terminal, and outputs a ground open detection signal informing that the ground terminal of the chip is of an open state of not being connected to the external ground terminal.
11. The integrated circuit according to claim 9 ,
wherein the power state determination circuit operates as a power supply voltage detection circuit having a function of detecting a power supply voltage of the power terminal, and detects that the ground terminal is open based on whether the voltage of the power terminal is lower than a reference voltage.
12. The integrated circuit according to claim 9 ,
wherein the first and second transistors are N-channel MOS transistors, and
wherein the second transistor is provided between the first transistor and the ground terminal, and a gate is connected to a drain terminal of the first transistor.
13. The integrated circuit according to claim 9 ,
wherein the first and second transistors are N-channel MOS transistors, and
wherein the second transistor is provided between the first transistor and the input terminal, and a gate is connected to a source terminal of the first transistor.
14. The integrated circuit according to claim 9 ,
wherein the first and second transistors are N-channel MOS transistors, and
wherein the second transistor is provided between the first transistor and the input terminal, and a gate is connected to a gate of the first transistor.
15. The integrated circuit according to claim 9 ,
wherein the first and second transistors are N-channel MOS transistors provided in different P-type well regions, and
wherein the second transistor is provided between the first transistor and the input terminal, and a gate is connected to a source terminal of the first transistor.
16. The integrated circuit according to claim 9 ,
wherein the first and second transistors are N-channel MOS transistors provided in different P-type well regions, and
wherein the second transistor is provided between the first transistor and the ground terminal, and a gate is connected to a drain terminal of the first transistor.