Adjustable delayer, method for delaying an input signal and polar transmitter

1. An adjustable delayer for adjustably delaying an input signal based on a delay adjustment input information describing a desired delay, to obtain an output signal, the adjustable delayer comprising:

a plurality of series-connected tunable delay circuits, wherein a first of the tunable delay circuits is configured to receive the input signal;

a closed-loop control circuit configured to provide a first delay tuning information to tune a combined delay of the plurality of tunable delay circuits to fulfill a predetermined condition; and

a combiner configured to combine the first delay tuning information with a second delay tuning information, that is based on the delay adjustment input information, to obtain a combined delay tuning information;

wherein the adjustable delayer is configured to tune a delay of one or more of the tunable delay circuits based on the combined delay tuning information; and

wherein the adjustable delayer is configured to provide the output signal based on one or more signals present at one or more outputs of one or more of the tunable delay circuits.

2. The adjustable delayer according to claim 1 , wherein the adjustable delayer is configured to tune a first subset of the tunable delay circuits and a second subset of the tunable delay circuits such that delays of the tunable delay circuits of the first subset increase with increasing values of the second delay tuning information and such that delays of the tunable delay circuits of the second subset of the tunable delay circuits reduce with increasing values of the second delay tuning information in the presence of a constant first delay tuning information.

3. The adjustable delayer according to claim 2 , wherein the adjustable delayer is configured to tune the first subset of the tunable delay circuits and the second subset of the tunable circuits such that delays of the tunable delay circuits of the first subset and delays of the tunable delay circuits of the second subset change in the same direction with a variation of the first delay tuning information in the presence of a constant second delay tuning information.

4. The adjustable delayer according to claim 2 , wherein the adjustable delayer is configured to tune the first subset of the tunable delay circuits and the second subset of the tunable delay circuits in such a manner that a magnitude of a change of a combined delay of the first subset of tunable delay circuits caused by a given variation of the second delay tuning information differs from a magnitude of a change of a combined delay of the second subset of tunable delay circuits caused by the given variation of the second delay tuning information by no more than 20%, and

wherein a sign of the change of the combined delay of the first subset of tunable delay circuits is opposite to a sign of the change of the combined delay of the second subset of tunable delay circuits.

5. The adjustable delayer according to claim 1 , wherein the closed-loop control circuit is configured to provide the first delay tuning information to obtain a predetermined phase relationship between the input signal and a delayed version of the input signal that is provided at an output of the series-connected tunable delay circuits.

6. The adjustable delayer according to claim 1 , wherein the adjustable delayer comprises a delay locked loop,

wherein the delay locked loop comprises the closed-loop control circuit and the plurality of series-connected tunable delay circuits; and

wherein the first delay tuning information is a control quantity of the delay locked loop.

7. The adjustable delayer according to claim 6 , wherein the second delay tuning information is a disturbance quantity of the delay locked loop, and

wherein the adjustable delayer is configured to introduce into the delay locked loop a compensation, in order to at least partially compensate for the disturbance quantity.

8. The adjustable delayer according to claim 7 , wherein the closed loop control circuit is configured to receive the delay adjustment input information and use the delay adjustment input information in order to at least partially compensate for the disturbance quantity.

9. The adjustable delayer according to claim 8 , wherein the adjustable delayer is configured to combine the delay adjustment input information with a phase detector reference signal or with a phase detector result signal or with an internal signal of a loop filter, in order to at least partially compensate for the disturbance quantity.

10. The adjustable delayer according to claim 1 , wherein the adjustable delayer comprises a selector configured to select a tap of the plurality of series-connected tunable delay circuits based on the delay adjustment input information and provide the output signal on the basis of a signal present at the selected tap, to coarsely adjust a delay between the input signal and the output signal; and

wherein the adjustable delayer is configured to vary the second delay tuning information based on the delay adjustment input information, to finely adjust the delay between the input signal and the output signal.

11. The adjustable delayer according to claim 1 , wherein the closed-loop control circuit comprises a phase detector configured to compare a phase of the input signal with a phase of a delayed version of the input signal that is provided at an output or a tap of the plurality of series-connected tunable delay elements, and provide a phase detector result signal; and

wherein the closed-loop control circuit comprises a loop filter configured to receive the phase detector result signal and provide, on the basis thereof, the first delay tuning information.

12. The adjustable delayer according to claim 11 , wherein the adjustable delayer comprises a first digital combiner configured to add a value representing the second delay tuning information to a value representing the first delay tuning information, to obtain a first digital-to-analog converter input information; and

wherein the adjustable delayer comprises a second digital combiner configured to subtract a value representing the second delay tuning information, or a positively scaled version thereof, from the value representing the first delay tuning information, to obtain a second digital-to-analog converter input information;

wherein the adjustable delayer comprises a first digital-to-analog converter configured to provide a first analog control quantity for tuning a delay of a first subset of the tunable delay circuits on the basis of the first digital-to-analog converter input information and a second digital-to-analog converter configured to provide a second analog control quantity for tuning a delay of the second subset of the tunable delay circuits on the basis of the second digital-to-analog converter input information.

13. The adjustable delayer according to claim 1 , wherein the tunable delay circuits are inverter stages or driver stages comprising a current limiter circuit,

wherein the current limiter circuit is configured to adjustably limit an output current of the inverter stage or driver stage based on the combined delay tuning information.

14. The adjustable delayer according to claim 1 , wherein the adjustable delayer is configured to derive the second delay tuning information from one or more least significant bits of the delay adjustment input information.

15. The adjustable delayer according to claim 1 , wherein the adjustable delayer is configured to derive a coarse delay adjustment information from one or more most significant bits of the delay adjustment input information.

16. The adjustable delayer according to claim 1 , wherein the adjustable delayer is configured to temporarily break a closed loop comprising the closed-loop control circuit, the series connection of a plurality of the tunable delay elements and the combiner; and

wherein the adjustable delayer is configured to provide the output signal using a first subset of the tunable delay elements during a period of time in which the closed loop is broken, and

wherein the adjustable delayer is configured to use the second subset of the tunable delay circuits for another functionality, other than providing the output signal, during the period of time in which the control loop is broken; and

wherein the adjustable delayer is configured to re-establish a closed loop comprising the closed-loop control circuit, the series connection of the plurality of tunable delay circuits and the combiner after the temporary break of the closed loop, to thereby update the first delay tuning information.

17. The adjustable delayer according to claim 16 , wherein the adjustable delayer is configured to periodically break the closed loop of the closed-loop control circuit.

18. The adjustable delayer according to claim 16 , wherein the adjustable delayer is configured to determine or calibrate a gain of a delay adjustment of the tunable delay circuits during the period of time in which the closed loop is broken.

19. The adjustable delayer according to claim 18 , wherein the adjustable delayer is configured to vary a delay of the tunable delay circuits of the second plurality of tunable delay circuits and to monitor a change of a phase of a signal provided using the tunable delay circuits of the second plurality of tunable delay circuits, to thereby obtain an information about a gain of the delay adjustment of the tunable delay circuits.

20. A method for delaying an input signal based on a delay adjustment input information describing a desired delay, to obtain an output signal, the method comprising:

providing a first delay tuning information to tune a combined delay of a plurality of tunable circuits, that are connected together in series, to fulfill a predetermined condition;

combining the first delay tuning information with a second delay tuning information, that is based on the delay adjustment input information, to obtain a combined delay tuning information;

tuning a delay of one or more of the tunable delay circuits based on the combined delay tuning information;

wherein the output signal is obtained on the basis of the input signal using one or more of the tunable delay circuits tuned based on the combined delay tuning information.

21. The method according to claim 20 , wherein a first subset of the tunable delay circuits and a second subset of the tunable delay circuits are tuned such that delays of the tunable delay circuits of the first subset increase with increasing values of the second delay tuning information, and such that delays of the tunable delay circuits of the second subset reduce with increasing values of the second delay tuning information in the presence of a constant first delay tuning information.

22. The adjustable delayer according to claim 21 , wherein the delays of the tunable delay circuits of the first subset and the delays of the tunable delay circuits of the second subset are tuned based on the second delay tuning information such that a combined delay of the first subset of tunable delay circuits and of the second subset of tunable delay circuits varies by less than 10% over a maximum variation range of the second delay tuning information.

23. The method according to claim 20 , wherein the method further comprises selecting a tap of the series connection of the plurality of tunable delay circuits based on the delay adjustment input information and providing the output signal on the basis of a signal present at the selected tap, to coarsely adjust a delay between the input signal and the output signal; and

wherein the method comprises varying the second delay tuning information based on the delay adjustment input information, to finely adjust the delay between the input signal and the output signal.

24. The method according to claim 20 , wherein the method comprises using a closed loop to provide the first delay tuning information, and

wherein the method comprises temporarily breaking the closed loop,

wherein the output signal is provided using a first subset of the tunable delay circuits during a period of time in which the closed loop is broken, and wherein a second subset of the tunable delay circuits is used for another functionality, other than providing the output signal, during the period of time in which the closed loop is broken; and

wherein the method comprises re-establishing a closed loop to thereby update the first delay tuning information.

25. An adjustable delayer for adjustably delaying an input signal based on a delay adjustment input information describing a desired delay, to obtain an output signal, the adjustable delayer comprising:

a delay line comprising a first sub-delay line and a second sub-delay line connected in series;

a delay locked loop, wherein the first sub-delay line and the second sub-delay line are included in the delay locked loop,

a closed-loop control circuit configured to provide a first delay tuning signal to change delays of the first sub-delay line and of the second sub-delay line in the same direction in response to deviation of an actual phase shift between a reference signal and an output signal of the second sub-delay line from a predetermined target phase shift; and

a signal provider configured to provide a second delay tuning signal and a third delay tuning signal to change delays of the first sub-delay line and of the second sub-delay line in opposite directions based on the delay adjustment input information;

wherein the first sub-delay line is configured to receive the input signal; and

wherein the adjustable delayer is configured to provide the output signal on the basis of an output signal of the first sub-delay line or on the basis of a signal at a tap of the first sub-delay line, or

wherein the adjustable delayer is configured to provide the output signal on the basis of an output signal of the second sub-delay line or on the basis of a signal at a tap of the second sub-delay line.

26. The adjustable delayer according to claim 25 , wherein the first sub-delay line and the second sub-delay line and the signal provider are configured such that an overall delay along the first sub-delay line and the second sub-delay line remains substantially constant, within a tolerance of 1%, over a full range of the delay adjustment input information.

27. A polar transmitter for providing a phase modulated output signal based on a phase modulation information, the polar transmitter comprising:

an oscillator configured to provide an unmodulated carrier signal or an incompletely modulated signal; and

an adjustable delayer configured to adjustably delay an input signal based on a delay adjustment input information describing a desired delay, to obtain an output signal, the adjustable delayer comprising:

a series connection of a plurality of tunable delay circuits, wherein a first of the tunable delay circuits is configured to receive the input signal;

a closed-loop control circuit configured to provide a first delay tuning information to tune a combined delay of the plurality of tunable delay circuits to fulfill a predetermined condition; and

a combiner configured to combine the first delay tuning information with a second delay tuning information, that is based on the delay adjustment input information, to obtain a combined delay tuning information;

wherein the adjustable delayer is configured to tune a delay of one or more of the tunable delay circuits based on the combined delay tuning information; and

wherein the adjustable delayer is configured to provide the output signal based on one or more signals present at one or more outputs of one or more of the tunable delay circuits;

wherein the adjustable delayer is configured to receive the unmodulated or partially modulated carrier signal as the input signal;

wherein the adjustable delayer is configured to receive the phase modulation information as the second delay tuning information or to derive the second delay tuning information from the phase modulation information;

wherein the output signal of the adjustable delayer is the phase modulated output signal;

wherein the polar transmitter is configured to apply a phase modulation to the oscillator, such that the output signal of the oscillator, that is provided to an input of the adjustable delayer, is phase modulated based on the phase modulation information; and

wherein the polar transmitter is configured to apply an additional phase modulation to the output signal of the oscillator using the adjustable based on the phase modulation information, to obtain the phase modulated output signal.

28. The polar transmitter according to claim 27 , wherein the oscillator is part of a phase locked loop, and wherein the phase locked loop is adjusted based on the phase modulation information.

29. An adjustable delayer for adjustably delaying an input signal based on a delay adjustment input information describing a desired delay, to obtain an output signal, the adjustable delayer comprising:

a plurality of series-connected tunable delay circuits, wherein a first of the tunable delay circuits is configured to receive the input signal;

a closed-loop control circuit configured to provide a first delay tuning information to tune a combined delay of the plurality of tunable delay circuits to fulfill a predetermined condition; and

a combiner configured to combine the first delay tuning information with a second delay tuning information that is based on the delay adjustment input information to obtain a combined delay tuning information;

wherein the adjustable delayer is configured to tune a delay of one or more of the tunable delay circuits based on the combined delay tuning information; and

wherein the adjustable delayer is configured to provide the output signal based on one or more signals present at one or more outputs of one or more of the tunable delay circuits;

wherein the adjustable delayer is configured to tune a first subset of the tunable delay circuits and a second subset of the tunable delay circuits such that delays of the tunable delay circuits of the first subset increase with increasing values of the second delay tuning information and such that delays of the tunable delay circuits of the second subset of the tunable delay circuits reduce with increasing values of the second delay tuning information in the presence of a constant first delay tuning information;

wherein the adjustable delayer is configured to tune the first subset of the tunable delay circuits and the second subset of the tunable circuits such that delays of the tunable delay circuits of the first subset increase with increasing values of the first delay tuning information and such that delays of the tunable delay circuits of the second subset increase with increasing values of the first delay tuning information in the presence of a constant second delay tuning information;

wherein the adjustable delayer is configured to tune the first subset of the tunable delay circuits and the second subset of the tunable delay circuits in such a manner that a magnitude of a change of a combined delay of the first subset of tunable delay circuits caused by a given variation of the second delay tuning information differs from a magnitude of a change of a combined delay of the second subset of tunable delay circuits caused by the given variation of the second delay tuning information by no more than 20%, and

wherein a sign of the change of the combined delay of the first subset of tunable delay circuits is opposite to a sign of the change of the combined delay of the second subset of tunable delay circuits;

wherein the adjustable delayer comprises a delay locked loop,

wherein the delay locked loop comprises the closed-loop control circuit and the plurality of series-connected tunable delay circuits; and

wherein the first delay tuning information is a control quantity of the delay locked loop;

wherein the adjustable delayer comprises a selector configured to select a tap of the series connection of the plurality of tunable delay circuits based on the delay adjustment input information and provide the output signal on the basis of a signal present at the selected tap, to coarsely adjust a delay between the input signal and the output signal; and

wherein the adjustable delayer is configured to vary the second delay tuning information based on the delay adjustment input information, to finely adjust the delay between the input signal and the output signal.

30. A polar transmitter for providing a phase modulated output signal based on a phase modulation information, the polar transmitter comprising:

a variable phase oscillator configured to provide an incompletely modulated signal,

wherein the variable phase oscillator is configured to adjust a phase of the incompletely modulated signal based on the phase modulation information or based on a component of the phase modulation information; and

an adjustable delayer configured to adjustably delay the incompletely modulated signal based on the phase modulation information or based on a component of the phase modulation information, to obtain the phase modulated output signal.

31. The polar transmitter according to claim 30 , wherein the polar transmitter is configured to apply a phase modulation to the variable phase oscillator, such that the output signal of the variable phase oscillator, that is provided to an input of the adjustable delayer, is phase modulated based on the phase modulation information, and

wherein the polar transmitter is configured to apply an additional phase modulation to the output signal of the variable phase oscillator using the adjustable delayer based on the phase modulation information, to obtain the phase modulated output signal.

32. The polar transmitter according to claim 31 , wherein the variable phase oscillator is part of a phase locked loop, and wherein the phase locked loop is adjusted based on the phase modulation information.

33. The polar transmitter according to claim 30 , wherein the polar transmitter is configured to split a coarse phase modulation and a fine phase modulation between the variable phase oscillator and the adjustable delayer, such that one out of the variable phase oscillator and the adjustable delayer performs a coarse phase modulation and that the other out of the variable phase oscillator and the adjustable delayer performs a fine phase modulation.