Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.
1. A nonvolatile semiconductor memory device comprising:
a memory cell array having a plurality of memory cells arranged in a matrix, which include a plurality of selecting transistors and a plurality of memory cell transistors, each of the plurality of memory cell transistors being connected in series to respective one of the plurality of selecting transistors;
a first bit line connecting to drains of a first set of the plurality of the selecting transistors arranged in a first column;
a second bit line connecting to drains of a second set of the plurality of the selecting transistors arranged in a second column;
a first plurality of word lines coupled to a first row decoder controlling a first potential of the first plurality of word lines, the first plurality of word lines includes:
(i) a first word line connecting to gate electrodes of a first set of the plurality of memory cell transistors arranged in a first row and
(ii) a second word line connecting to gate electrodes of a second set of the plurality of memory cell transistors arranged in a second row;
a second plurality of word lines coupled to a second row decoder controlling a second potential of the second plurality of word lines, the second plurality of word lines includes:
(i) a third word line connecting to gate electrodes of a third set of the plurality of selecting transistors arranged in a third row and
(ii) a fourth word line connecting to gate electrodes of a fourth set of the plurality of selecting transistors arranged in a fourth row;
a plurality of source lines coupled to a third row decoder controlling a third potential of the plurality of source lines, the plurality of source lines include:
(i) a first source line connecting to sources of the first set of the plurality of memory cell transistors arranged in the first row and
(ii) a second source line connecting to sources of the second set of the plurality of memory cell transistors arranged m the second row;
a column decoder coupled to the first and second bit lines and controlling a potential of said bit lines,
wherein the column decoder includes a low withstand voltage transistor having a gate insulation film whose thickness is thinner than a thickness of a gate insulating film of a transistor included in either the first row decoder or the third row decoder,
the second row decoder includes a low withstand voltage transistor having a gate insulation film whose thickness is thinner than the thickness of the gate insulating film of the transistor included in either the first row decoder or the third row decoder and wherein
information is written into a selected one of the memory cells by applying a first voltage which gradually rises selectively to one of the first word lines by the voltage application circuit; and applying a second voltage to one of the source lines by the second row decoder.
2. The nonvolatile semiconductor memory device according to claim 1 , wherein
the memory cell transistor includes a floating gate formed over a semiconductor substrate with a tunnel insulation film formed therebetween;
a gate electrode formed over the floating gate with an insulation film formed therebetween; a first impurity diffused layer formed in the semiconductor substrate on one side of the floating gate and forming a source; and
a second impurity diffused layer formed in the semiconductor substrate on the other side of the floating gate.
3. The nonvolatile semiconductor memory device according to claim 1 , wherein
the memory cell transistor includes a gate electrode formed over a semiconductor substrate with a charge storage layer formed therebetween;
a first impurity diffused layer formed in the semiconductor substrate on one side of the gate electrode and forming a source; and
a second impurity diffused layer formed in the semiconductor substrate on the other side of the gate electrode.
4. The nonvolatile semiconductor memory device according to claim 3 , wherein
the charge storage layer includes a first silicon oxide film formed over the semiconductor substrate, a silicon nitride film formed over the first silicon oxide film, and a second silicon oxide film formed over the silicon nitride film.
5. The nonvolatile semiconductor memory device according to claim 1 , wherein
the first row decoder controls at once the potential of said plurality of first word lines.
6. The nonvolatile semiconductor memory device according to claim 1 , wherein the information is written into a selected one of the memory cells by applying the second voltage at the fixed time of an interval.
7. The nonvolatile semiconductor memory device according to claim 6 , wherein the information is written into a selected one of the memory cells by applying the second voltage in pluses.