Method of manufacturing semiconductor device
View Patent ↗A method of manufacturing a semiconductor device is provided. The method includes forming a gate electrode on a semiconductor substrate; forming a dopant implantation area in the semiconductor substrate by implanting a dopant in the semiconductor substrate, using the gate electrode as a mask; forming sidewalls on the gate electrode; forming a first recess by etching the semiconductor substrate, using the gate electrode and the sidewalls as a mask; forming a second recess by removing the dopant implantation area positioned below the sidewalls; and forming a source area and a drain area by causing a semiconductor material to grow in the first recess and the second recess.
1. A method of manufacturing a semiconductor device, the method comprising:
forming a first gate electrode above a semiconductor substrate;
forming a dopant implantation area in the semiconductor substrate by implanting a dopant in the semiconductor substrate, using the first gate electrode as a mask;
forming sidewall spacers on the first gate electrode;
forming a first recess having a first depth and exposing the dopant implantation area within the first recess at least at a bottom of the first recess by etching the semiconductor substrate, using the first gate electrode and the sidewall spacers as a mask;
forming a second recess having a second depth shallower than the first depth and exposing the dopant implantation area within the second recess by removing a part of the dopant implantation area positioned below the sidewall spacers; and
forming a source area and a drain area by causing a semiconductor material to grow in the first recess and the second recess,
wherein each of the first depth and the second depth is a distance taken from a bottom surface of the first gate electrode towards a bottom of the semiconductor substrate along a direction perpendicular to the bottom surface of the first gate electrode.
2. The method according to claim 1 , wherein
the forming the second recess is performed in an epitaxial growth device, and
the forming the source area and the drain area are performed in the epitaxial growth device.
3. The method according to claim 1 , wherein
the semiconductor substrate is formed by a silicon substrate, and
the dopant is arsenic or phosphorus.
4. The method according to claim 3 , wherein the forming the second recess includes selectively etching the dopant implantation area with respect to the semiconductor substrate, by using gas including chlorine gas.
5. The method according to claim 3 , wherein the forming the dopant implantation area includes implanting arsenic as the dopant, by a dose amount within a range of 1×10 14 cm −2 to 1×10 16 cm −2 .
6. The method according to claim 3 , wherein the forming the source area and the drain area forms the source area and the drain area to include silicon germanium.
7. The method according to claim 3 , further comprising:
forming a silicon layer on the source area and the drain area.
8. The method according to claim 1 , wherein
the semiconductor device includes a P-type transistor and an N-type transistor,
the dopant implantation area includes a P-type transistor formation area to form the P-type transistor, and an N-type transistor formation area to form the N-type transistor, and
the forming the dopant implantation area includes implanting a dopant in both the P-type transistor formation area and the N-type transistor formation area.
9. The method according to claim 1 , wherein
the forming the dopant implantation area includes forming a first dopant implantation area in the semiconductor substrate, and forming a second dopant implantation area on the first dopant implantation area,
the forming the first recess exposes the first dopant implantation area within the first recess, and
the forming the second recess having the second depth exposes the first dopant implantation area within the second recess by removing the second dopant implantation area positioned below the sidewall spacers.
10. The method according to claim 9 , wherein each of the first dopant implantation area and the second dopant implantation area is formed by an ion implantation.
11. The method according to claim 10 , wherein the first dopant implantation area is formed by a first ion implantation with a first energy by a first dose amount, and the second dopant implantation area is formed by a second ion implantation with a second energy lower than the first energy by a second dose amount higher than the first dose amount.
12. The method according to claim 1 , wherein
the forming the first gate electrode includes forming a second gate electrode above the semiconductor substrate, and
the forming the first recess makes a height of the first gate electrode lower than a height of the second gate electrode.
13. The method according to claim 12 , wherein
the semiconductor device includes a P-type transistor and an N-type transistor,
the dopant implantation area includes a P-type transistor formation area to form the P-type transistor, and an N-type transistor formation area to form the N-type transistor, and
the forming the dopant implantation area includes implanting a dopant in both the P-type transistor formation area and the N-type transistor formation area.
14. The method according to claim 1 , wherein the forming the first recess forms the first recess to the first depth shallower than a depth of the dopant implantation area so that the dopant implantation area remains after the first recess is formed.
15. The method according to claim 1 , wherein
the forming the second recess is performed in an epitaxial growth device, and
the forming the source area and the drain area are performed in the epitaxial growth device, continuously to the forming the second recess.