Semiconductor memory device and method for driving semiconductor memory device
View Patent ↗A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix; a plurality of word lines commonly coupling the control gates of the plural memory cell transistors present in a identical first direction; a plurality of source lines commonly coupling the sources of the plural memory cell transistors present in the identical first direction; a plurality of bit lines commonly coupling the drains of the plural memory cell transistors present in a identical second direction intersecting the first direction; a first transistor having a drain coupled to the source line; a second transistor having a drain coupled to a source of the first transistor, a gate coupled to the word line and a source grounded; and a control line commonly coupling the gates of the plural first transistors.
1. A method for driving a semiconductor memory device including a plurality of memory cell transistors arranged in a matrix;
a plurality of word lines coupling the control gates of the plural memory cell transistors present in the identical one direction;
a plurality of source lines coupling the sources of the plural memory cell transistors present in the identical one direction;
a plurality of bit lines coupling the drains of the plural memory cell transistors present in the identical other direction intersecting said one direction;
a first transistor having a drain coupled to the source line;
a second transistor having a drain coupled to a source of the first transistor, a gate coupled to the word line and a source grounded; and
control lines coupling the gates of the plural first transistors, said method comprising:
turning the plural first transistors on-states via the control line;
applying a first voltage to one of the bit lines coupled to the drain of one of the memory cell transistors and applying a second voltage selectively to one of the word lines coupled to the gate of said one memory cell transistor; and
reading information stored in said one memory cell transistor, based on a current flowing in said one of the bit lines.
2. The method for driving a semiconductor memory device according to claim 1 , wherein
said first voltage is incessantly applied to the plural bit lines including said one bit lines.
3. The method for driving a semiconductor memory device according to claim 1 ,
when the first voltage is applied to said one bit line, the first voltage is applied selective to said one bit line of the plural bit lines.
4. A method for driving a semiconductor memory device including a plurality of memory cell transistors arranged in a matrix;
a plurality of word lines coupling the control gates of the plural memory cell transistors present in the identical one direction;
a plurality of source lines coupling the sources of the plural memory cell transistors present in the identical one direction;
a plurality of bit lines coupling the drains of the plural memory cell transistors present in the identical other direction intersecting said one direction;
a first transistor having a drain coupled to the source line;
a second transistor having a drain coupled to a source of the first transistor, a gate coupling to the word line and a source grounded; and
a control line coupling the gates of the plural first transistors, said method comprising:
turning the plural first transistors off-states via the control line;
applying a third voltage to the plural word lines and applying a fourth voltage to the sources of the plural memory cell transistors to thereby erase information stored in the plural memory cell transistors.
5. The method for driving a semiconductor memory device according to claim 4 , wherein
when the fourth voltage is applied to the sources of the plural memory cell transistors, the fourth voltage is applied to the sources of the plural memory cell transistors via the wells where the plural memory cell transistors formed in.
6. The method for driving a semiconductor memory device according to claim 4 , wherein
when the fourth voltage is applied to the sources of the plural memory cell transistors, the fourth voltage is applied to the sources of the plural memory cell transistors via the source lines.