Flash memory cell arrays having dual control gates per memory cell charge storage element
View Patent ↗A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least two control gate lines. The control gate lines are preferably positioned between floating gates to be coupled with sidewalls of floating gates. The memory cell coupling ratio is desirably increased, as a result. Both control gate lines on opposite sides of a selected row of floating gates are usually raised to the same voltage while the second control gate lines coupled to unselected rows of floating gates immediately adjacent and on opposite sides of the selected row are kept low. The control gate lines can also be capacitively coupled with the substrate in order to selectively raise its voltage in the region of selected floating gates. The length of the floating gates and the thicknesses of the control gate lines can be made less than the minimum resolution element of the process by forming an etch mask of spacers.
1. A method of making a memory cell array on a semiconductor substrate, comprising:
providing a well on a top surface of the substrate by doping;
forming a rectangular array of isolated columns and rows of floating gates from doped polysilicon with a first layer of dielectric therebetween; and
forming isolated control gates extending across the substrate area as word lines perpendicular to said columns, each word line being postitioned between rows of the floating gates in a manner that opposing sidewalls of the floating gates are capacitively coupled with walls of the control gates on opposite sides thereof through a second layer of dielectric and bottom surfaces of the control gates are capacitively coupled with the surface of the substrate over the well through a third layer of dielectric.
2. The method of claim 1 , wherein forming the floating gates includes:
depositing a layer of conductive floating gate material over the first layer of dielectric across the surface area of the substrate,
depositing a first type of dielectric material over the floating gate material layer,
removing portions of the first type of dielectric material to leave strips elongated in a direction of the columns and having widths and spaces between them in a direction of the rows according to a minimum resolvable element size,
forming spacers of a second type of dielectric along side walls of the strips of the first type of dielectric material in a manner leaving spaces between the spacers in the direction of the columns that are less than the minimum resolvable element size, and
removing portions of the first type of dielectric material and of the floating gate material layer between the spacers, thereby defining the floating gates with lengths and spaces between them in the direction of the columns that are less than the minimum resolvable element size.
3. The method of claim 2 , wherein removing portions of the first type of dielectric material includes forming a mask thereover with widths of strips and spaces therebetween according to the minimum resolvable element size, and thereafter isotropically sideways etching the first type of dielectric material through the mask in a manner that partially removes the first type of dielectric material under the mask strips, thereby to form the strips of the first type of dielectric material with widths that are less than the minimum resolvable element size.
4. The method of either of claim 1 or 2 , additionally comprising, prior to forming control gates, of forming trenches in the substrate surface between the floating gates in the direction of the columns, and wherein forming the control gates includes forming the control gates to extend into said trenches with electrical insulation therebetween.
5. The method of either of claim 1 or 2 , wherein forming the control gates includes forming a bottom portion of the control gates from doped polysilicon material and thereafter forming a top portion of the control gates from a metal or silicide material in contact with the doped polysilicon material.
6. The method of either of claim 1 or 2 , wherein forming the control gates includes forming from tungsten or molybdenum.
7. The method of claim 5 , wherein forming the top portion of the control gates includes forming a continuous layer of said metal or silicide over the array, and thereafter performing a chemical-mechanical-polishing operation to remove an amount of said continuous layer that leaves the top portions of the control gates within the trenches and isolated from each other.