IP Library Granted Patent US 8,674,478
Granted Patent B2
US 8,674,478 · App. 13/212,541 · Granted Mar 18, 2014

Semiconductor device having capacitor with upper electrode whose circumference is made long

Inventor: Hirotoshi Tachibana (Kawasaki, JP)
Assignee: Fujitsu Semiconductor Limited
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Quick Facts
Patent No.
US 8,674,478
App. No.
13/212,541
Granted
Mar 18, 2014
Kind
B2
Abstract

A capacitor is formed over a semiconductor substrate. The capacitor includes a lower electrode, a capacitor dielectric film and an upper electrode in this order recited, and has an area S equal to or larger than 1000 μm 2 and L/S equal to or larger than 0.4 μm −1 , where S is an area of a capacitor region in which the lower and upper electrodes face each other across the dielectric film, and L is a total length of a circumference line of the capacitor region.

Claims (12)

1. A semiconductor device comprising:

a semiconductor substrate; and

a capacitor formed over the semiconductor substrate, comprising a lower electrode, a capacitor dielectric film and an upper electrode stacked in an order recited,

wherein the upper electrode is included within the lower electrode as viewed in plan, and a plan shape of the upper electrode is a rectangle, and the upper electrode has an area S equal to or larger than 1000 μm 2 and a length of shorter side W of the plan shape of the upper electrode is equal to or less than 5 μm.

2. A semiconductor device comprising:

a semiconductor substrate; and

a capacitor formed over the semiconductor substrate, comprising a lower electrode, a capacitor dielectric film and an upper electrode stacked in an order recited, the upper electrode being located within the lower electrode as viewed in plan, the upper electrode and the capacitor dielectric film comprising a plurality of patterns isolated from each other, and each width of the patterns being equal to or less than 5 μm,

wherein the patterns of the upper electrode are electrically connected with each other.

3. The semiconductor device according to claim 2 further comprising:

an interlayer insulating film over the upper electrode comprising the patterns;

conductive plugs in the interlayer insulating film, the conductive plugs being electrically connected to the patterns of the upper electrode, respectively; and

a wiring over the interlayer insulating film, the wiring being connected to the conductive plugs.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR MEMORY SOLUTION LIMITED
Reel/Frame 053195/0249 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
Continuity (3)
Division 12405565 · Mar 17, 2009
Continuation PCTJP2006319122 · Sep 27, 2006
Related Publication 20110298091A1 · Dec 8, 2011