Semiconductor integrated circuit device and data processor system
View Patent ↗A semiconductor integrated circuit device includes a first high-speed serial interface circuit which has one differential serial data channel and a second high-speed serial interface circuit which has a plurality of differential serial data channels, the first high-speed serial interface circuit performs interface with the outside for control information, and a control circuit performs an internal operation on the basis of the control information. Both of the high-speed serial interface circuits share a RAM for storage of display data information. Whether the data information to be supplied to the RAM is received by using the first high-speed serial interface circuit or the second high-speed serial interface circuit is determined by the control circuit in accordance with the control information that is input to the first high-speed serial interface circuit.
1. A data processor system comprising:
a baseband processor configured as a host microcomputer to perform a reproducing process of audio data from an audio port and an image process of photographing data from a camera port;
an accelerator coupled to the baseband processor;
a display driving control device coupled to the baseband processor and the accelerator; and
a display device coupled to the display driving control device,
wherein the display driving control device includes:
a first high-speed serial interface circuit coupled to the baseband processor and which has one differential serial data channel;
a second high-speed serial interface circuit coupled to the accelerator and which has a plurality of differential serial data channels;
a control circuit which controls an internal operation based on control information input to the first high-speed serial interface circuit from the baseband processor;
a RAM to receive data that is input to the first high-speed serial interface circuit from the baseband processor and data that is input to the second high-speed serial interface circuit from the accelerator; and
a display driver circuit which generates a display driving signal, based on data read from the RAM, to output to the display device,
wherein whether the first high-speed serial interface circuit or the second high-speed serial interface circuit is used when receiving the data to be supplied to the RAM is determined by the control circuit based on the control information input to the first high-speed serial interface circuit.
2. The data processor system according to claim 1 , further comprising:
a microphone coupled to an A/D converter; and
a speaker coupled to a D/A converter.
3. The data processor system according to claim 1 ,
wherein the baseband processor is coupled to a high-frequency circuit, and the accelerator is a microcomputer which executes a command issued from the baseband processor.
4. The data processor system according to claim 3 mounted in a mobile communication terminal device.
5. The data processor system according to claim 1 , wherein the control circuit uses a first frame synchronization signal input from the baseband processor in a RAM operation for the data that is input to the first high-speed serial interface circuit, and uses a second frame synchronization signal reproduced by using strobe information in a RAM operation for the data that is input to the second high-speed serial interface circuit, the strobe information being input from the accelerator.
6. The data processor system according to claim 5 , wherein the first high-speed serial interface circuit is a mobile digital data interface circuit which inputs the data and the control information in synchronization with a differential strobe signal.
7. The data processor system according to claim 6 , wherein the second high-speed serial interface circuit is a mobile video interface circuit which inputs the data and the strobe information in synchronization with a clock signal.
8. The data processor system according to claim 1 , wherein when supplying the data input to the first high-speed serial interface circuit to the RAM, the control circuit starts reproduction of a second frame synchronization signal in response to a switching instruction associated with the control information, and starts writing of the data input to the second high-speed serial interface circuit into the RAM in synchronization with the second frame synchronization signal after writing of data for one frame in synchronization with a first frame synchronization signal is completed.
9. The data processor system according to claim 8 , wherein when supplying the data input to the second high-speed serial interface circuit to the RAM, the control circuit starts writing of the data input to the first high-speed serial interface circuit into the RAM in synchronization with the first frame synchronization signal after writing of data for one frame in synchronization with the second frame synchronization signal is completed in response to a switching instruction associated with the control information.