IP Library Granted Patent US 8,273,630
Granted Patent B2
US 8,273,630 · App. 13/238,336 · Granted Sep 25, 2012

Method for manufacturing semiconductor device

Assignee: Fujitsu Semiconductor Limited
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Quick Facts
Patent No.
US 8,273,630
App. No.
13/238,336
Granted
Sep 25, 2012
Kind
B2
Abstract

A method for manufacturing a semiconductor device includes forming a silicon substrate having first and second surfaces, the silicon substrate including no oxide film or an oxide film having a thickness no greater than 100 nm, forming a first oxide film at least on the second surface of the silicon substrate, forming a first film by covering at least the first surface, forming a mask pattern on the first surface by patterning the first film, forming a device separating region on the first surface by using the mask pattern as a mask, forming a gate insulating film on the first surface, forming a gate electrode on the first surface via the gate insulating film, forming a source and a drain one on each side of the gate electrode, and forming a wiring layer on the silicon substrate while maintaining the first oxide film on the second surface.

Claims (30)

1. A method for manufacturing a semiconductor device, comprising:

forming a substrate having first and second surfaces, the substrate including no oxide film or an oxide film having a thickness no greater than 100 nm;

forming a first film by covering at least the first surface;

forming a first oxide film on the first and second surfaces;

removing the first oxide film formed on the first surface;

forming a mask pattern on the first surface by patterning the first film;

forming a device separating region on the first surface by using the mask pattern as a mask;

forming a gate insulating film on the first surface;

forming a gate electrode on the first surface via the gate insulating film;

forming a source and a drain on each side of the gate electrode; and

forming a wiring layer on the substrate while leaving the first oxide film on the second surface.

2. The method as claimed in claim 1 , wherein forming the gate insulating film is performed by placing a plurality of the substrates in a vertical furnace and thermally processing the plurality of the substrates.

3. The method as claimed in claim 2 , wherein the thermal processing is performed subsequent to the removing of the first oxide film.

4. The method as claimed in claim 1 , wherein forming the device separating region includes

forming a device separating groove on the first surface by using the mask pattern;

depositing a silicon oxide film on the first surface; and

removing the silicon oxide film except at an area of the first surface where the device separating groove is formed;

wherein the silicon oxide film is removed by using a chemical mechanical polishing process and a HydroFluoric (HF) process.

5. The method as claimed in claim 1 ,

wherein the first film is a single layer film including a poly-silicon film.

6. The method as claimed in claim 1 , wherein the first oxide film has a thickness no less than 200 nm.

7. The method as claimed in claim 1 , wherein forming the wiring layer includes forming a Cu wiring layer.

8. The method as claimed in claim 1 , wherein the first film is a single layer film including a silicon oxide film.

9. The method as claimed in claim 1 , wherein the first film is a single layer film including a silicon nitride film or a silicon oxynitride film.

10. The method as claimed in claim 1 , wherein the first film is a single layer film including an amorphous silicon film.

11. The method as claimed in claim 1 , wherein the first film is a multilayer film including two or more of a poly-silicon film, a silicon oxide film, a silicon nitride film, an amorphous silicon film, and a silicon oxynitride film.

12. The method as claimed in claim 1 , wherein the substrate is a silicon substrate.

13. The method as claimed in claim 1 , wherein the substrate is a 300 mm wafer.

14. The method as claimed in claim 1 , wherein a size of the substrate is that of a 300mm wafer.

15. The method as claimed in claim 1 , wherein the wiring layer includes a multilayered wiring structure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2015
From: FUJITSU SEMICONDUCTOR LIMITED
To: SOCIONEXT INC.
Reel/Frame 035508/0637 →
Priority Claims (1)
JP 2008-163797 · Jun 23, 2008 · national
Continuity (2)
Division 12468265 · May 19, 2009
Related Publication 20120009752A1 · Jan 12, 2012