IP Library Granted Patent US 8,278,177
Granted Patent B2
US 8,278,177 · App. 13/240,303 · Granted Oct 2, 2012

Semiconductor device and method of manufacturing the same

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,278,177
App. No.
13/240,303
Granted
Oct 2, 2012
Kind
B2
Abstract

A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer.

Claims (44)

1. A method of manufacturing a semiconductor device, comprising:

forming a gate insulating film on a silicon substrate;

forming a gate electrode on the gate insulating film;

forming impurity diffused layers in the silicon substrate by ion-implanting with the gate electrode as a mask;

forming a trench in the impurity diffused layers;

forming a first crystal layer on a bottom of the trench, the first crystal layer located within or higher than a same plane with an interface between the silicon substrate and the gate insulating film; and

forming a second crystal layer on the first crystal layer;

forming a silicide layer on the second crystal layer;

wherein said second crystal layer has a lattice constant closer to a lattice constant of silicon than a lattice constant of the first crystal layer.

2. A method of manufacturing a semiconductor device, comprising:

forming a gate insulating film on a silicon substrate;

forming a gate electrode on the gate insulating film;

forming impurity diffused layers in the silicon substrate by ion-implanting with the gate electrode as a mask;

forming a trench in the impurity diffused layers;

forming a first crystal layer on a bottom of the trench, the first crystal layer located within or higher than a same plane with an interface between the silicon substrate and the gate insulating film; and

forming a second crystal layer on the first crystal layer;

forming a silicide layer on the second crystal layer;

wherein the first crystal layer is constituted of silicon germanium having a first germanium concentration, and the second crystal layer is constituted of silicon germanium having a second germanium concentration which is lower than the first germanium concentration.

3. The method of manufacturing a semiconductor device according to claim 2 , wherein

the first germanium concentration is 20 atom % or higher, and the second germanium concentration is lower than 20 atom %.

4. The method of manufacturing a semiconductor device according to claim 2 , wherein

the first crystal layer is formed at a first growing temperature, and the second crystal layer is formed at a second growing temperature which is higher than the first growing temperature.

5. The method of manufacturing a semiconductor device, comprising:

forming a gate insulating film on a silicon substrate;

forming a gate electrode on the gate insulating film;

forming impurity diffused layers in the silicon substrate by ion-implanting with the gate electrode as a mask;

forming a trench in the impurity diffused layers;

forming a first crystal layer on a bottom of the trench, the first crystal layer located within or lower than a same plane with an interface between the silicon substrate and the gate insulating film; and

forming a second crystal layer on the first crystal layer;

forming a silicide layer on the second crystal layer;

wherein the first crystal layer has a lattice constant closer to a lattice constant of silicon than a lattice constant of the second crystal layer.

6. The method of manufacturing a semiconductor device, comprising:

forming a gate insulating film on a silicon substrate;

forming a gate electrode on the gate insulating film;

forming impurity diffused layers in the silicon substrate by ion-implanting with the gate electrode as a mask;

forming a trench in the impurity diffused layers;

forming a first crystal layer on a bottom of the trench, the first crystal layer located within or lower than a same plane with an interface between the silicon substrate and the gate insulating film; and

forming a second crystal layer on the first crystal layer;

forming a silicide layer on the second crystal layer;

wherein the first crystal layer is constituted of silicon germanium having a first germanium concentration, and the second crystal layer is constituted of silicon germanium having a second germanium concentration which is higher than the first germanium concentration.

7. The method of manufacturing a semiconductor device according to claim 6 , wherein:

the first germanium concentration is lower than 20 atom %, and the second germanium concentration is 20 atom % or higher.

8. A method of manufacturing a semiconductor device according to claim 6 , wherein:

the first crystal layer is formed at a first growing temperature, and the second crystal layer is formed at a second growing temperature which is lower than the first growing temperature.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
MERGER Recorded May 24, 2023
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU LIMITED
Reel/Frame 064221/0545 →
CHANGE OF NAME AND CHANGE OF ADDRESS Recorded Jul 16, 2020
From: AIZU FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053481/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: AIZU FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053209/0468 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →