Interactive graphical pin assignment
View Patent ↗A design tool provides interactive graphical pin assignment. In one embodiment, the design tool identifies layout restrictions of a configurable processing device that includes a plurality of pins. The design tool further provides an interactive visual representation of a pin assignment that accommodates the layout restrictions and a user input.
1. A method comprising:
receiving an indication of a configurable processing device comprising a plurality of pins;
automatically determining, by a processor, pin assignments for a subset of the plurality of pins according to pin prioritization data;
if an automatically determined pin assignment fails, presenting a pin assignment graphical user interface to allow a user to perform manual pin assignments through drag and drop operations; and
generating an embedded application for implementation on the configurable processing device based on the pin assignments.
2. The method of claim 1 , wherein the pin assignments comprise assignments of signals associated with drivers of the embedded application to the plurality of pins.
3. The method of claim 1 , wherein the pin prioritization data comprises a pin prioritization table in metadata stored in a data module coupled to the processor.
4. The method of claim 1 , wherein the pin prioritization data restricts the assignment of pins to the subset of the plurality of pins.
5. The method of claim 1 , wherein the pin prioritization data comprises an order in which the pin assignments for the subset of the plurality of pins are determined.
6. The method of claim 5 , wherein the automatic determination of pin assignments fails if all of the subset of pins in the pin prioritization data are in conflict with a current pin assignment.
7. An apparatus comprising:
a processor; and
a memory coupled to the processor, the memory comprising:
a design module to generate an embedded application for implementation on a configurable processing device comprising a plurality of pins, wherein the design module comprises a pin interconnection evaluator to automatically determine pin assignments for a subset of the plurality of pins according to pin prioritization data, wherein if the automatic determination of pin assignments fails, the design module to present a pin assignment graphical user interface to allow a user to perform a manual pin assignment through a drag and drop operation, and wherein the embedded application is generated based on the pin assignments.
8. The apparatus of claim 7 , wherein the pin assignments comprise assignments of signals associated with drivers of the embedded application to the plurality of pins.
9. The apparatus of claim 7 , wherein the pin prioritization data comprises a pin prioritization table in metadata stored in a data module of the memory.
10. The apparatus of claim 7 , wherein the pin prioritization data restricts the assignment of pins to the subset of the plurality of pins.
11. The apparatus of claim 7 , wherein the pin prioritization data comprises an order in which the pin assignments for the subset of the plurality of pins are determined.
12. The apparatus of claim 7 , wherein the automatic determination of pin assignments fails if all of the subset of pins in the pin prioritization data are in conflict with a current pin assignment.
13. A non-transitory machine-readable store medium including a plurality of instructions which when executed perform a method comprising:
receiving an indication of a configurable processing device comprising a plurality of pins;
automatically determining, by a processor, pin assignments for a subset of the plurality of pins according to pin prioritization data;
if an automatically determined pin assignment fails, presenting a pin assignment graphical user interface to allow a user to perform a manual pin assignment through a drag and drop operation; and
generating an embedded application for implementation on the configurable processing device based on the pin assignments.
14. The non-transitory machine-readable store medium of claim 13 , wherein the pin assignments comprise assignments of signals associated with drivers of the embedded application to the plurality of pins.
15. The non-transitory machine-readable store medium of claim 13 , wherein the pin prioritization data comprises a pin prioritization table in metadata stored in a data module coupled to the processor.
16. The non-transitory machine-readable store medium of claim 13 , wherein the pin prioritization data restricts the assignment of pins to the subset of the plurality of pins.
17. The non-transitory machine-readable store medium of claim 13 , wherein the pin prioritization data comprises an order in which the pin assignments for the subset of the plurality of pins are determined.
18. The non-transitory machine-readable store medium of claim 13 , wherein the automatic determination of pin assignments fails if all of the subset of pins in the pin prioritization data are in conflict with a current pin assignment.