SIMD memory circuit and methodology to support upsampling, downsampling and transposition

1. A configurable memory circuit for a Single Instruction, Multiple Data (SIMD) Digital Signal Processor (DSP) in a wireless communications system, for generating output vectors from sequential input data vectors, comprising:

a rotate-and-distribute unit configured to rotate and distribute input data elements of the input data vectors;

a two-dimensional register file configured to receive and store vectors generated by the rotate-and-distribute unit;

a write controller configured to control writing of the vectors in the two-dimensional register file by generating write-enable signals for cells of the two-dimensional register file; and

a read controller configured to generate the output vectors by reading on a per column basis selected cells of the two-dimensional register file,

wherein, the write controller is further configured to control the writing in the two-dimensional register file such that at least two of the input data elements pertaining to a same vector among the input data vectors are stored in cells on different rows and different columns of the two-dimensional register file.

2. The memory circuit of claim 1 , wherein the rotate-and-distribute unit distributes the input data elements of the input data vectors to all columns of the two-dimensional register file.

3. The memory circuit of claim 2 , wherein the rotate-and-distribute unit further comprises: a single rotate unit that performs a vertical translation of a pattern in the two-dimensional register file, based on a software pipeline stage.

4. The memory circuit of claim 1 , wherein the rotate-and-distribute unit further comprises:

a plurality of rotate units, each corresponding to one among multiple columns of the two-dimensional register file and rotating one of the input vector with a column-specific rotation.

5. The memory circuit of claim 4 , further comprising:

a plurality of left-over-addition units connected to the plurality of rotate units and configured to preserve data elements from a previous store operation when the data elements from a previous store operation exist.

6. The memory circuit of claim 5 , wherein at least one of the plurality of left-over-addition units combines a previously rotated input vector with a current rotated input vector.

7. The memory circuit of claim 5 , wherein the write controller generates row and column enable signals, from which write-enable signals are derived by doing a logical AND operation on the row and column enable signals specific to the cell.

8. The memory circuit of claim 4 , wherein the read controller selects a row in the two-dimensional register file, to be received in the output vector.

9. The memory circuit of claim 1 , wherein the input data elements are of a same word length.

10. The memory circuit of claim 1 , wherein the write controller supports input data elements of differing word lengths.

11. The memory circuit of claim 1 , wherein the input data vectors are of a constant vector length.

12. The memory circuit of claim 1 , wherein the read and write controllers have state-machines for generating their respective control signals, based on parameters received from the SIMD DSP.

13. The memory circuit of claim 1 , wherein the read and write controllers translate configuration patterns received from the SIMD DSP to respective control patterns.

14. The memory circuit of claim 13 , wherein the configuration patterns are preloaded into a configuration memory.

15. The memory circuit of claim 6 , wherein the read controller selects P elements from P+E column outputs stored in the two-dimensional register file and aligns them in the output vector.

16. The memory circuit of claim 15 , wherein the rotate-and-distribute units have P+E logical column output vectors of which elements are stored in P+E columns of the two-dimensional register file, according to a predetermined pattern.

17. A method for generating output vectors from sequential input data vectors utilizing a configurable memory circuit for a Single Instruction, Multiple Data (SIMD) Digital Signal Processor (DSP) in a wireless communications system, the configurable memory circuit having a rotate-and-distribute unit, a two-dimensional register file, a write controller and a read controller, the method comprising:

rotating and distributing input data elements of the input data vectors by the rotate-and-distribute unit;

receiving and storing vectors generated by the rotate-and-distribute unit in the two-dimensional register file, writing therein being controlled by the writing controller which generates write-enable signals for cells of the two-dimensional register file; and

generating the output vectors by the read controller which selects on a per column basis data elements stored in the two-dimensional register file,

wherein the write controller controls the writing in the two-dimensional register file such that at least two of the input data elements pertaining to a same vector among the input data vectors are stored in cells on different rows and different columns of the two-dimensional register file.

18. The method of claim 17 , wherein the rotating and distributing comprises: distributing a rotated input vector among the input vectors to all columns of the two-dimensional register file.

19. The method of claim 18 , wherein the rotating and distributing further comprises:

vertical translating a pattern in the two-dimensional register file, according to a software pipeline stage.

20. The method of claim 17 , wherein the rotating and distributing comprises:

rotating one of the input vectors with a column-specific rotation each corresponding to one or multiple columns of the two-dimensional register file, using a plurality of rotate units.

21. The method of claim 20 , further comprising:

preserving data elements from a previous store operation when the data elements from the previous store operation exist, using a plurality of left-over-addition units connected to the plurality of rotate units.

22. The method of claim 21 , wherein the plurality of left over addition units combines a previously rotated input vector with a current rotated input vector.

23. The method of claim 22 , further comprising:

generating row and column enable signals from which the write-enable signals are derived by doing a logical AND operation on the row and column enable signals specific to the cell by the write controller.

24. The method of claim 20 , wherein the read controller selects a row in the two-dimensional register file, to be received in the output vector.

25. The method of claim 17 , wherein the input data elements are of a same word length.

26. The method of claim 17 , wherein the write controller supports input data elements of differing word lengths.

27. The method of claim 17 , wherein the input data vectors are of a constant vector length.

28. The method of claim 17 , wherein the read and write controllers have state-machines for generating their respective control signals, based on parameters received from the SIMD DSP.

29. The method of claim 17 , wherein the read and write controllers translate configuration patterns received from the SIMD DSP to respective control patterns.

30. The method of claim 29 , where the configuration patterns are preloaded into a configuration memory.

31. The method of claim 22 , wherein the read controller selects P elements from P+E column outputs stored in the two-dimensional register file and aligns them into the output vector.

32. The method of claim 31 , wherein P+E logical column output vectors of which elements are stored in the P+E columns of the two-dimensional register file, according to a predetermined pattern.