Methods and apparatus for direct synthesis of RF signals using delta-sigma modulator
View Patent ↗Methods and apparatus are provided for direct synthesis of RF signals using a delta-sigma modulator. An RF signal is synthesized from an input signal by quantizing the input signal using a quantizer, such as a one bit quantizer; determining a quantization error associated with the quantizer; generating an error prediction value using an error predictive filter, wherein the error predictive filter comprises one or more filter zeroes on a unit circle for one or more desired frequencies of f 1 , f 2 , . . . f n and one or more filter poles having a magnitude inside the unit circle and a frequency substantially equal to the one or more desired frequencies of f 1 , f 2 , . . . f n ; and subtracting the error prediction value from the input signal. The filter poles have a magnitude that reduces a boost provided out-of-band.
1. A method for synthesizing an RF signal from an input signal, comprising:
quantizing said input signal using a quantizer;
determining a quantization error associated with said quantizer;
generating an error prediction value using an error predictive filter, wherein said error predictive filter comprises a plurality of filter zeroes on a unit circle for one or more desired frequencies of f 1 , f 2 , . . . f N and a corresponding plurality of filter poles having a magnitude inside said unit circle and a frequency substantially equal to said one or more desired frequencies of f 1 , f 2 , . . . f N ; and
subtracting said error prediction value from said input signal.
2. The method of claim 1 , wherein said filter poles have a magnitude that reduces an out-of-band boosting of noise.
3. The method of claim 1 , wherein said filter zeroes are fixed for said one or more desired frequencies of f 1 , f 2 , . . . f N .
4. The method of claim 1 , wherein said filter zeroes are variable and said one or more desired frequencies of f 1 , f 2 , . . . f N are programmable values.
5. The method of claim 1 , wherein said step of determining a quantization error further comprises the step of comparing an input to said one bit quantizer to an output of said one bit quantizer.
6. The method of claim 1 , wherein said quantizer is a one bit quantizer.
7. A delta-sigma modulator, comprising:
a quantizer for quantizing an input signal;
a comparison circuit for determining a quantization error associated with said quantizer;
an error predictive filter to generate an error prediction value, wherein said error predictive filter comprises a plurality of filter zeroes on a unit circle for one or more desired frequencies of f 1 , f 2 , . . . f N and a corresponding plurality of filter poles having a magnitude inside said unit circle and a frequency substantially equal to said one or more desired frequencies of f 1 , f 2 , . . . f N ; and
an adder for subtracting said error prediction value from said input signal.
8. The delta-sigma modulator of claim 7 , wherein said filter poles have a magnitude that reduces an out-of-band boosting of noise.
9. The delta-sigma modulator of claim 7 , wherein said filter zeroes are fixed for said one or more desired frequencies of f 1 , f 2 , . . . f N .
10. The delta-sigma modulator of claim 7 , wherein said filter zeroes are variable and said one or more desired frequencies of f 1 , f 2 , . . . f N are programmable values.
11. The delta-sigma modulator of claim 7 , wherein said comparison circuit obtains said quantization error by comparing an input to said one bit quantizer to an output of said one bit quantizer.
12. The delta-sigma modulator of claim 7 , wherein said quantizer is a one bit quantizer.
13. An integrated circuit, comprising:
a delta-sigma modulator, comprising:
a quantizer for quantizing an input signal;
a comparison circuit for determining a quantization error associated with said quantizer;
an error predictive filter to generate an error prediction value, wherein said error predictive filter comprises a plurality of filter zeroes on a unit circle for one or more desired frequencies of f 1 , f 2 , . . . f N and a corresponding plurality of filter poles having a magnitude inside said unit circle and a frequency substantially equal to said one or more desired frequencies of f 1 , f 2 , . . . f N ; and
an adder for subtracting said error prediction value from said input signal.
14. The integrated circuit of claim 13 , wherein said filter poles have a magnitude that reduces an out-of-band boosting of noise.
15. The integrated circuit of claim 13 , wherein said filter zeroes are fixed for said one or more desired frequencies of f 1 , f 2 , . . . f N .
16. The integrated circuit of claim 13 , wherein said filter zeroes are variable and said one or more desired frequencies of f 1 , f 2 , . . . f N are programmable values.
17. The integrated circuit of claim 13 , wherein said comparison circuit obtains said quantization error by comparing an input to said one bit quantizer to an output of said one bit quantizer.
18. The integrated circuit of claim 13 , wherein said quantizer is a one bit quantizer.