Shifting cell voltage based on grouping of solid-state, non-volatile memory cells
View Patent ↗Cells of a solid-state, non-volatile memory are assigned to one of a plurality of groups. Each group is defined by expected symbols stored in the cells in view of actual symbols read from the cells. Based on cell counts within the groups, it can be determined that a shift in a reference voltage will reduce a collective bit error rate of the cells. The shift can be applied to data access operations affecting the cells.
1. A method comprising:
assigning cells of a solid-state, non-volatile memory to one of a plurality of groups, wherein each group is defined by expected symbols stored in the cells in view of actual symbols read from the cells;
based on cell counts within the groups, determining that a shift in a reference voltage will reduce a collective bit error rate of the cells; and
applying the shift to data access operations affecting the cells;
wherein the data access operations comprise a program verify operation.
2. The method of claim 1 , wherein the data access operations further comprise read operations.
3. The method of claim 2 , wherein the assigning of the cells to the groups and the determining and applying of the shift are performed iteratively two or more times.
4. The method of claim 1 , wherein the assigning of the cells to the groups and the determining and applying of the shift are performed iteratively two or more times.
5. The method of claim 1 , wherein the reference voltage comprises a boundary voltage associated with at least two soft data channels, and wherein determining that the shift will reduce the collective bit error rate of the cells further comprises determining that the shift will reduce error rates consistently in the two or more soft data channels.
6. The method of claim 1 , wherein the assignment of cells to the groups are based on previously performed read operations, and wherein the shift is further modified based on one or more conditions affecting the cells, the one or more conditions comprising any of program-erase cycles, data retention time, and disturb.
7. A method comprising:
assigning cells of a solid-state, non-volatile memory to one of a plurality of groups, wherein each group is defined by expected symbols stored in the cells in view of actual symbols read from the cells;
based on cell counts within the groups, determining that a shift in a reference voltage will reduce a collective bit error rate of the cells; and
applying the shift to data access operations affecting the cells;
wherein determining that the shift will reduce the collective bit error rate of the cells comprises evaluating an expression comprising a function p(b,r) that refers to a number of cells having expected symbol values of b being read in voltage region r, wherein r represents regions adjacent the reference voltage.
8. The method of claim 7 , wherein the expression is multiplied by a factor that is dependent on the noise characteristics of the flash memory.
9. An apparatus comprising:
a controller capable of being coupled to cells of a solid-state, non-volatile memory, the controller configured to perform:
assigning each of the cells to one of a plurality of groups, wherein each group is defined by expected symbols stored in the cells in view of actual symbols read from the cells;
based on cell counts within the groups, determining that a shift in a reference voltage will reduce a collective bit error rate of the cells; and
applying the shift to data access operations affecting the cells;
wherein the data access operations comprise a program verify operation.
10. The apparatus of claim 9 , wherein the data access operations further comprise read operations.
11. The apparatus of claim 10 , wherein the assigning of the cells to the groups and the determining and applying of the shift are performed iteratively two or more times.
12. The apparatus of claim 9 , wherein the assigning of the cells to the groups and the determining and applying of the shift are performed iteratively two or more times.
13. The apparatus of claim 9 , wherein the reference voltage comprises a boundary voltage associated with at least two soft data channels, and wherein determining that the shift will reduce the collective bit error rate of the cells further comprises determining that the shift will reduce error rates consistently in the two or more soft data channels.
14. The apparatus of claim 9 , wherein the assignment of cells to the groups are based on previously performed read operations, and wherein the adjustments/shifts are further modified based on one or more conditions affecting the cells, the one or more conditions comprising any of program-erase cycles, data retention time, and disturb.