HIGH ELECTRON MOBILITY TRANSISTOR STRUCTURE AND METHOD
Embodiments of the present disclosure describe structural configurations of an integrated circuit (IC) device such as a high electron mobility transistor (HEMT) switch device and method of fabrication. The IC device includes a buffer layer formed on a substrate, a channel layer formed on the buffer layer to provide a pathway for current flow in a transistor device, a spacer layer formed on the channel layer, a barrier layer formed on the spacer layer, the barrier layer including aluminum (Al), nitrogen (N), and at least one of indium (In) or gallium (Ga), a gate dielectric directly coupled with the spacer layer or the channel layer, and a gate formed on the gate dielectric, the gate being directly coupled with the gate dielectric. Other embodiments may also be described and/or claimed.
1 . An apparatus comprising:
a buffer layer formed on a substrate, the buffer layer being epitaxially coupled with the substrate;
a channel layer formed on the buffer layer to provide a pathway for current flow in a transistor device, the channel layer being epitaxially coupled with the buffer layer;
a spacer layer formed on the channel layer, the spacer layer being epitaxially coupled with the channel layer;
a barrier layer formed on the spacer layer, the barrier layer being epitaxially coupled with the spacer layer, the barrier layer including aluminum (Al), nitrogen (N), and at least one of indium (In) or gallium (Ga);
a gate dielectric directly coupled with the spacer layer or the channel layer; and
a gate formed on the gate dielectric, the gate being directly coupled with the gate dielectric.
2 . The apparatus of claim 1 , wherein:
the buffer layer includes aluminum gallium nitride (Al x Ga 1-x N), where x is a value between 0 and 1 that represents relative quantities of aluminum and gallium;
the channel layer includes gallium nitride (GaN);
the spacer layer includes aluminum nitride (AlN); and
the barrier layer includes indium aluminum nitride (In y Al 1-y N), where y is a value between 0 and 1 that represents relative quantities of indium and aluminum.
3 . The apparatus of claim 2 , wherein:
the buffer layer has a thickness between 0.1 microns and 2 microns and x has a value between 0.05 and 1;
the channel layer has a thickness between 50 angstroms and 150 angstroms;
the spacer layer has a thickness between 5 angstroms and about 30 angstroms; and
the barrier layer has a thickness between 50 angstroms and 150 angstroms and y has a value between 0.13 and 0.21.
4 . The apparatus of claim 1 , wherein:
the gate dielectric includes aluminum oxide (Al 2 O 3 ), silicon nitride (SiN), hafnium oxide (HfO 2 ), silicon dioxide (SiO 2 ) or silicon oxy-nitride (SiON); and
the gate dielectric has a thickness between 20 angstroms and 200 angstroms.
5 . The apparatus of claim 4 , wherein:
the gate is a T-shaped field plate gate; and
the gate includes nickel (Ni), platinum (Pt), iridium (Ir), molybdenum (Mo), or gold (Au).
6 . The apparatus of claim 1 , further comprising:
a source formed on the barrier layer; and
a drain formed on the barrier layer, wherein each of the source and the drain extend through the barrier layer and the spacer layer into the channel layer.
7 . The apparatus of claim 6 , wherein:
the source is an ohmic contact;
the drain is an ohmic contact; and
a shortest distance between the drain and the gate is greater than a shortest distance between the source and the gate.
8 . The apparatus of claim 1 , further comprising:
the substrate, the substrate including silicon (Si), silicon carbide (SiC), sapphire (Al 2 O 3 ), gallium nitride (GaN), or aluminum nitride (AlN).
9 . The apparatus of claim 1 , further comprising:
a dielectric layer formed on the barrier layer.
10 . The apparatus of claim 1 , wherein the gate is part of an enhancement mode (emode) high electron mobility transistor (HEMT) switch device.
11 . A method, comprising:
epitaxially depositing a buffer layer on a substrate;
epitaxially depositing a channel layer on the buffer layer, the channel layer to provide a pathway for current flow in a transistor device;
epitaxially depositing a spacer layer on the channel layer;
epitaxially depositing a barrier layer on the spacer layer, the barrier layer including aluminum (Al), nitrogen (N), and at least one of indium (In) or gallium (Ga);
selectively removing a portion of the barrier layer to expose the spacer layer;
depositing a gate dielectric material on the exposed spacer layer to form a gate dielectric that is directly coupled with the spacer layer; and
depositing a gate material on the gate dielectric to form a gate of the transistor device that is directly coupled with the gate dielectric.
12 . The method of claim 11 , wherein:
the buffer layer includes aluminum gallium nitride (Al x Ga 1-x N), where x is a value between 0 and 1 that represents relative quantities of aluminum and gallium;
the channel layer includes gallium nitride (GaN);
the spacer layer includes aluminum nitride (AlN); and
the barrier layer includes indium gallium aluminum nitride (In y Ga z Al 1-y-z N), where y and z are values between 0 and 1 that represents relative quantities of indium and gallium.
13 . The method of claim 12 , wherein:
the buffer layer has a thickness between 0.1 microns and 2 microns and x has a value between 0.05 and 1;
the channel layer has a thickness between 50 angstroms and 150 angstroms;
the spacer layer has a thickness between 5 angstroms and about 30 angstroms; and
the barrier layer has a thickness between 50 angstroms and 150 angstroms and y has a value between 0.13 and 0.21.
14 . The method of claim 11 , wherein:
the portion of the barrier layer is selectively removed using an etch process;
the gate dielectric is deposited using an atomic layer deposition (ALD) process;
the gate dielectric includes aluminum oxide (Al 2 O 3 ), silicon nitride (SiN), hafnium oxide (HfO 2 ), silicon dioxide (SiO 2 ) or silicon oxy-nitride (SiON); and
the gate dielectric has a thickness between 20 angstroms and 200 angstroms.
15 . The method of claim 14 , wherein:
the gate is a T-shaped field plate gate; and
the gate includes nickel (Ni), platinum (Pt), iridium (Ir), molybdenum (Mo), or gold (Au).
16 . The method of claim 11 , further comprising:
forming a source on the barrier layer; and
forming a drain on the barrier layer,
wherein each of the source and the drain extend through the barrier layer and the spacer layer into the channel layer,
wherein a shortest distance between the drain and the gate is greater than a shortest distance between the source and the gate, and
wherein each of the source and the drain is an ohmic contact.
17 . The method of claim 11 , further comprising:
providing the substrate, the substrate including silicon (Si), silicon carbide (SiC), sapphire (Al 2 O 3 ), gallium nitride (GaN), or aluminum nitride (AlN).
18 . The method of claim 11 , further comprising:
forming a dielectric layer on the barrier layer.
19 . The method of claim 11 , wherein the channel layer is configured to provide a pathway for current flow in an enhancement mode (e-mode) high electron mobility transistor (HEMT) switch device.
20 . The method of claim 11 , wherein each of the buffer layer, the channel layer, the spacer layer, and the barrier layer is epitaxially deposited by molecular beam epitaxy (MBE), atomic layer epitaxy (ALE), chemical beam epitaxy (CBE) or metal-organic chemical vapor deposition (MOCVD).