IP Library Granted Patent US 8,247,283
Granted Patent B2
US 8,247,283 · App. 13/283,312 · Granted Aug 21, 2012

Manufacture of semiconductor device with stress structure

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Quick Facts
Patent No.
US 8,247,283
App. No.
13/283,312
Granted
Aug 21, 2012
Kind
B2
Abstract

A method for manufacturing a semiconductor device includes the steps of (a) forming a gate electrode on a silicon substrate, through a gate insulating film; (b) forming a lamination of an insulating film and a sacrificial film having different etching characteristics on the silicon substrate, covering the gate electrode, and anisotropically etching the lamination to form side wall spacers on side walls of the gate electrode and the gate insulating film; (c) implanting impurities into the silicon substrate on both sides of the side wall spacers; (d) etching the silicon substrate and the sacrificial film to form recesses in the silicon substrate, and to change a cross sectional shape of each of the side wall spacers to approximately an L-shape; (e) epitaxially growing Si—Ge-containing crystal in the recesses; and (f) depositing an insulating film containing stress, covering the side wall spacers.

Claims (17)

1. A method for manufacturing a complementary type semiconductor device comprising:

(a) forming gate electrodes in a PMOS region and an NMOS region on a silicon substrate, through a gate insulating film;

(b) forming an insulating layer including a silicon nitride film and a silicon oxide film formed thereon on the silicon substrate, covering the gate electrodes, and further forming a sacrificial layer on the insulating layer;

(c) anisotropically etching the sacrificial film to leave the sacrificial film only on side walls of the gate electrode in a side wall spacer shape;

(d) covering the NMOS region with a mask, further anisotropically etching the insulating film to pattern the insulating layer by using the sacrificial film as an etching mask to expose silicon surface in the PMOS region;

(e) removing the mask covering the NMOS region, etching regions of the silicon substrate with exposed silicon surface in the PMOS region to form recesses, and removing the sacrificial film while leaving the silicon oxide film which has been covered with the sacrificial film;

(f) epitaxially growing Si—Ge-containing crystal in the recesses;

(g) anisotropically etching the silicon nitride film not covered with the silicon oxide film in the NMOS region;

(h) forming a silicon nitride film having tensile stress above the NMOS region; and

(i) forming another silicon nitride film having compressive stress above the PMOS region.

2. The method for manufacturing a complementary type semiconductor device according to claim 1 , wherein said sacrificial film is a silicon film, and said step (b) is CVD.

3. The method for manufacturing a complementary type semiconductor device according to claim 1 , wherein said step (b) comprises:

(b-1) depositing said insulating film by CVD; and

(b-2) depositing a silicon nitride film on said insulating film by plasma-enhanced CVD.

4. The method for manufacturing a complementary type semiconductor device according to claim 1 , wherein said step (e) is performed by chemical dry etching using CF 4 /O 2 as etching gas.

5. The method for manufacturing a complementary type semiconductor device according to claim 1 , wherein said step (e) is performed by anisotropic dry etching and wet etching.

6. The method for manufacturing a complementary type semiconductor device according to claim 1 , wherein a thickness of a layer epitaxially grown at said step (f) is greater than a depth of said recess, and the layer bulges upper than a surface of said silicon substrate.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
MERGER Recorded May 24, 2023
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU LIMITED
Reel/Frame 064221/0545 →
CHANGE OF NAME AND CHANGE OF ADDRESS Recorded Jul 16, 2020
From: AIZU FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053481/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: AIZU FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053209/0468 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →