IP Library Granted Patent US 8,247,284
Granted Patent B2
US 8,247,284 · App. 13/283,331 · Granted Aug 21, 2012

Manufacture of semiconductor device with stress structure

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Quick Facts
Patent No.
US 8,247,284
App. No.
13/283,331
Granted
Aug 21, 2012
Kind
B2
Abstract

A method for manufacturing a semiconductor device includes the steps of (a) forming a gate electrode on a silicon substrate, through a gate insulating film; (b) forming a lamination of an insulating film and a sacrificial film having different etching characteristics on the silicon substrate, covering the gate electrode, and anisotropically etching the lamination to form side wall spacers on side walls of the gate electrode and the gate insulating film; (c) implanting impurities into the silicon substrate on both sides of the side wall spacers; (d) etching the silicon substrate and the sacrificial film to form recesses in the silicon substrate, and to change a cross sectional shape of each of the side wall spacers to approximately an L-shape; (e) epitaxially growing Si—Ge-containing crystal in the recesses; and (f) depositing an insulating film containing stress, covering the side wall spacers.

Claims (27)

1. A method for manufacturing a semiconductor device comprising:

(a) forming a gate insulating film and a gate electrode above a silicon substrate,

(b) forming a first insulating film above the silicon substrate, covering said gate electrode, forming a sacrificial film above the first insulating film, and etching the sacrificial film and the first insulating film to form side wall spacers on side walls of the gate electrode;

(c) implanting an impurity into the silicon substrate on both sides of the side wall spacers;

(d) etching the silicon substrate to form recesses in the silicon substrate, etching the sacrificial film included in the side wall spacers;

(e) forming Si—Ge-containing crystal in the recesses; and

(f) forming a second insulating film containing stress, covering the side wall spacers.

2. The method for manufacturing a semiconductor device according to claim 1 , wherein said step (d) etches said sacrificial film.

3. The method for manufacturing a semiconductor device according to claim 1 , wherein said insulating film includes a silicon nitride film.

4. The method for manufacturing a semiconductor device according to claim 3 , wherein said insulating film includes said silicon nitride film and a silicon oxide film formed thereon.

5. The method for manufacturing a semiconductor device according to claim 4 , further comprising:

(g) executing a wet process using HF between said steps (d) and (e) to remove an oxide film on surfaces of said recesses, while leaving said silicon oxide film of said side wall spacers.

6. The method for manufacturing a semiconductor device according to claim 1 , wherein said sacrificial film is an amorphous Si film.

7. The method for manufacturing a semiconductor device according to claim 6 , wherein said step (b) comprises a step of forming said amorphous Si film by CVD at a temperature not higher than 500° C.

8. The method for manufacturing a semiconductor device according to claim 1 , wherein said sacrificial film is a silicon nitride film.

9. The method for manufacturing a semiconductor device according to claim 8 , wherein said step (b) comprises a step of forming said silicon nitride film by plasma-enhanced CVD at a temperature not higher than 500° C.

10. The method for manufacturing a semiconductor device according to claim 1 , wherein said step (f) forms a silicon nitride film having compressive stress by plasma-enhanced CVD.

11. The method for manufacturing a semiconductor device according to claim 1 , wherein said step (d) performs dry etching using mixed gas of CF 4 and O 2 .

12. A method for manufacturing a semiconductor device comprising:

(a) forming a gate insulating film and a gate electrode above a silicon substrate;

(b) forming an insulating film including a silicon nitride above said silicon substrate, forming a silicon oxide film covering said insulating film, forming a sacrificial film of amorphous silicon or silicon nitride covering the silicon oxide film, and etching the sacrificial film, the silicon oxide film, and the insulating film to form side wall spacers on side walls of said gate electrode;

(c) implanting an impurity into said silicon substrate on both sides of said side wall spacers;

(d) etching said silicon substrate to form recesses in said silicon substrate, and etching said sacrificial film included in said side wall spacers and stopping the etching at said silicon oxide film;

(e) forming Si—Ge-containing crystal in said recesses; and

(f) forming a silicon nitride film containing stress, covering said side wall spacers.

13. The method for manufacturing a semiconductor device according to claim 12 , wherein said step (b) forms said insulating film by stacking from a lower side, a silicon oxide film, a silicon nitride film and a silicon oxide film.

14. The method for manufacturing a semiconductor device according to claim 13 , wherein said step (d) performs dry etching using mixed gas of CF 4 and O 2 .

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
MERGER Recorded May 24, 2023
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU LIMITED
Reel/Frame 064221/0545 →
CHANGE OF NAME AND CHANGE OF ADDRESS Recorded Jul 16, 2020
From: AIZU FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053481/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: AIZU FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053209/0468 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →