Prevention of ILD Loss in Replacement Gate Technologies by Surface Treatmen
When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, pronounced loss of the interlayer dielectric material may be avoided by inserting at least one surface modification process, for instance in the form of a nitridation process. In this manner, leakage paths caused by metal residues formed in the interlayer dielectric material may be significantly reduced.
1 . A method, comprising:
forming a dielectric layer above a gate electrode structure of a transistor, said gate electrode structure comprising a placeholder material;
performing a planarization process so as to remove a portion of said dielectric layer and provide a planarized surface;
performing a surface modification process so as to increase at least an etch resistivity of said planarized surface of said dielectric layer;
exposing a top surface of said placeholder material; and
performing an etch process so as to remove said placeholder material.
2 . The method of claim 1 , wherein said planarization process is performed so as to expose said top surface of said placeholder material.
3 . The method of claim 1 , wherein said gate electrode structure comprises a dielectric cap layer formed above said placeholder material and wherein performing said planarization process results in preserving a portion of said dielectric cap layer.
4 . The method of claim 3 , wherein performing said surface modification process results in a surface layer of increased etch resistivity forming an interface with material of said dielectric layer, wherein a height level of said interface is below a height level of an interface formed between said portion of said dielectric cap layer and said placeholder material.
5 . The method of claim 4 , further comprising performing a second planarization process so as to expose said top surface in the presence of said surface layer of increased etch resistivity.
6 . The method of claim 1 , wherein performing said surface modification process comprises applying a plasma ambient so as to incorporate a nitrogen species into exposed surface areas of said dielectric layer.
7 . The method of claim 1 , wherein performing said surface modification process comprises applying a chemical treatment based on a nitrogen-containing reagent.
8 . The method of claim 1 , wherein performing said etch process comprises performing a first etch step so as to remove a first portion of said placeholder material prior to performing said surface modification process.
9 . The method of claim 1 , further comprising performing at least one further surface modification process after forming at least a portion of said dielectric layer and prior to completely removing said placeholder material.
10 . A method, comprising:
forming a first portion of an interlayer dielectric material laterally adjacent to a gate electrode structure of a transistor, said gate electrode structure comprising a placeholder material and a dielectric cap layer formed above said placeholder material;
performing a surface modification process so as to form a modified surface layer on said first portion of said interlayer dielectric material;
forming a second portion of said interlayer dielectric material above said first portion;
forming an exposed top surface of said placeholder material by removing a part of at least said second portion and said dielectric cap layer; and
replacing said placeholder material with at least a metal-containing electrode material.
11 . The method of claim 10 , wherein forming said first portion of said interlayer dielectric material comprises depositing a dielectric material and removing a part thereof so as to adjust a height level of said first portion.
12 . The method of claim 11 , wherein said height level is adjusted so as to be at or below a height level of an interface formed by said dielectric cap layer and said placeholder material.
13 . The method of claim 10 , wherein forming said exposed top surface of said placeholder material comprises performing a chemical mechanical planarization process.
14 . The method of claim 13 , wherein forming said exposed surface of said placeholder material comprises performing a chemical mechanical planarization process.
15 . The method of claim 10 , wherein performing said surface modification process comprises incorporating a nitrogen species through a surface of said first portion of said interlayer dielectric material.
16 . The method of claim 10 , further comprising performing at least one further surface modification process after performing said surface modification process.
17 . The method of claim 16 , wherein said at least one further surface modification process is performed after forming said exposed top surface of said placeholder material.
18 . A method, comprising:
forming a dielectric material above and laterally adjacent to a gate electrode structure, said gate electrode structure comprising a placeholder material;
performing a process sequence so as to establish a planarized surface having a modified surface layer, said process sequence comprising performing a planarization process and performing a surface modification process;
repeating said process sequence at least once;
exposing a top surface of said placeholder material; and
replacing said placeholder material at least by a metal-containing electrode material.
19 . The method of claim 18 , wherein performing said surface modification process comprises incorporating a nitrogen species through said planarized surface of said interlayer dielectric material.
20 . The method of claim 19 , further comprising forming at least one of said gate electrode structure and said interlayer dielectric material so as to comprise a silicon and nitrogen containing material that is provided above said placeholder material.