IP Library Granted Patent US 8,542,031
Granted Patent B2
US 8,542,031 · App. 13/304,759 · Granted Sep 24, 2013

Method and apparatus for regulating a power supply of an integrated circuit

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Quick Facts
Patent No.
US 8,542,031
App. No.
13/304,759
Granted
Sep 24, 2013
Kind
B2
Abstract

Disclosed is a circuit for adjusting a voltage supplied to an IC by a power supply circuit that produces a regulated-output voltage based on an output-control signal generated by a resistive voltage divider. The circuit includes a PVT detector configured to generate an interface control signal and an interface circuit (i) connected to PVT detector and to the resistive voltage divider and (ii) configured to adjust its resistance in response to the interface control signal. Adjusting the resistance of the interface circuit causes the voltage of the output-control signal to be adjusted, thus causing the power supply circuit to adjust the regulated output voltage.

Claims (40)

1. An integrated circuit (IC) comprising:

a PVT detector configured to generate an interface control signal based on at least one of process, voltage, and temperature of the IC;

an interface circuit configured to produce a voltage control signal based on the interface control signal; and

a power supply circuit configured to produce a positive power supply voltage for the IC based on the voltage control signal,

wherein the interface circuit is configured to produce the voltage control signal by adjusting a resistance as a function of the interface control signal.

2. The circuit of claim 1 , wherein the resistance is an input resistance of a terminal of the IC.

3. The circuit of claim 1 , wherein:

said interface circuit comprises a plurality of switches, and

the interface control signal from the PVT detector controls said switches.

4. The circuit of claim 3 , wherein said interface circuit comprises a first plurality of resistors, each connected to a corresponding one of said switches.

5. The circuit of claim 4 , wherein a terminal on the IC is connected to a first predetermined voltage through at least one of the first plurality of resistors when its corresponding switch is closed.

6. The circuit of claim 4 , wherein said interface circuit comprises a second plurality of resistors, each connected to a corresponding one of the switches.

7. The circuit of claim 6 , wherein a terminal on the IC is connected to a second predetermined voltage through at least one of the second plurality of resistors when its corresponding switch is closed.

8. The circuit of claim 7 , wherein the first predetermined voltage is a maximum voltage and the second predetermined voltage is a minimum voltage.

9. The circuit of claim 1 , wherein the interface circuit comprises at least one active element configured to operate in a triode region.

10. The circuit of claim 1 , wherein the PVT detector comprises:

an oscillator that is configured to produce an oscillating signal that is a function of at least one of process, voltage, and temperature of the oscillator;

a converter connected to the oscillator and configured to convert the oscillating signal to a converted signal comprising one of a voltage signal and a current signal; and

a control circuit configured to produce the interface control signal based on the converted signal.

11. A method of controlling a positive supply voltage of an integrated circuit (IC), the method comprising:

a PVT detector generating an interface control signal based on at least one of process, voltage, and temperature of the IC;

an interface circuit producing a voltage control signal based on the interface control signal; and

a power supply circuit located on the IC producing the positive supply voltage for the IC based on the voltage control signal, wherein:

producing the voltage control signal comprises adjusting the resistance of the interface circuit, and

wherein at least one of:

(a) the resistance is an input resistance of a terminal of the IC;

(b) adjusting the resistance of the interface circuit comprises connecting at least one resistor to a first predetermined voltage in response to the interface control signal;

(c) adjusting the resistance of the interface circuit comprises controlling a resistance of at least one active element operating in a triode region, in response to the interface control signal; and

(d) said interface circuit comprises a plurality of switches, and the interface control signal from the PVT detector controls said switches.

12. The method of claim 11 , wherein the resistance is an input resistance of a terminal of the IC.

13. The method of claim 11 , wherein adjusting the resistance of the interface circuit comprises connecting at least one resistor to a first predetermined voltage in response to the interface control signal.

14. The method of claim 13 , wherein:

the at least one resistor comprises a first plurality of resistors, and

connecting the at least one resistor to the first predetermined voltage comprises connecting at least one of the first plurality of resistors to the first predetermined voltage.

15. The method of claim 14 , wherein adjusting the resistance of the interface circuit further comprises connecting at least one of a second plurality of resistors to a second predetermined voltage.

16. The method of claim 14 , wherein the first predetermined voltage is a maximum voltage and the second predetermined voltage is a minimum voltage.

17. The method of claim 11 , wherein adjusting the resistance of the interface circuit comprises controlling a resistance of at least one active element operating in a triode region, in response to the interface control signal.

18. The method of claim 11 , wherein:

said interface circuit comprises a plurality of switches, and

the interface control signal from the PVT detector controls said switches.

Assignments (12)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER IN THE INCORRECT US PATENT NO. 8,876,094 PREVIOUSLY RECORDED ON REEL 047351 FRAME 0384. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 049248/0558 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF THE MERGER PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0910. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047351/0384 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0910 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
CERTIFICATE OF FORMATION/CERTIFICATE OF CONVERSION Recorded Apr 30, 2013
From: AGERE SYSTEMS INC.
To: AGERE SYSTEMS LLC
Reel/Frame 030322/0453 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 28, 2011
From: AZIMI, KOUROS; MOBIN, MOHAMMAD S.; SHEETS, GREGORY W.; SMITH, LANE A.
To: AGERE SYSTEMS INC.
Reel/Frame 027282/0839 →