Semiconductor device periodically updating delay locked loop circuit
View Patent ↗Such a device is disclosed that includes a control circuit outputting a first clock signal having a first clock cycle in response to a first command signal and outputting a second clock signal having a second clock cycle in response to a second command signal, a first circuit controlled based on the first clock signal, and a second circuit controlled based on the second clock signal.
1. A semiconductor device comprising:
a control circuit outputting a first clock signal having a first clock cycle in response to a first command signal and outputting a second clock signal having a second clock cycle in response to a second command signal;
a first circuit controlled based on the first clock signal;
a second circuit controlled based on the second clock signal; and
a storage unit storing a first code indicating the first clock cycle and a second code indicating the second clock cycle, wherein
the control circuit generates the first clock signal based on the first code when the first command signal is supplied,
the control circuit generates the second clock signal based on the second code when the second command signal is supplied,
the control circuit includes an oscillator circuit that generates an oscillating signal,
each of the first and second codes specifies an oscillating cycle of the oscillating signal,
the control circuit generates the first clock signal based on the oscillating signal having an oscillating cycle corresponding to the first code when the first command signal is supplied, and
the control circuit generates the second clock signal based on the oscillating signal having an oscillating cycle corresponding to the second code when the second command signal is supplied.
2. The semiconductor device as claimed in claim 1 , wherein the oscillating cycle of the oscillating signal is controlled by a bias voltage that is decided based on the first and second codes.
3. The semiconductor device as claimed in claim 1 , wherein
the control circuit further includes a division circuit, and
the first and second clock signals are obtained by dividing the oscillating signal by the division circuit.
4. A semiconductor device comprising:
a control circuit outputting a first clock signal having a first clock cycle in response to a first command signal and outputting a second clock signal having a second clock cycle in response to a second command signal;
a first circuit controlled based on the first clock signal;
a second circuit controlled based on the second clock signal; and
a storage unit storing a first code indicating the first clock cycle and a second code indicating the second clock cycle, wherein
the control circuit generates the first clock signal based on the first code when the first command signal is supplied,
the control circuit generates the second clock signal based on the second code when the second command signal is supplied,
the control circuit includes an oscillator circuit that generates an oscillating signal and a division circuit that divides the oscillating signal to generate the first and second clock signals, and
a number of divisions of the division circuit is controlled according to the first and second codes.
5. A semiconductor device comprising:
a plurality of memory cells;
a control circuit including an oscillator circuit, wherein the oscillator circuit is configured to output a first clock signal in response to a first command signal and a second clock signal in response to a second command signal;
a first circuit configured to perform a refresh operation on the memory cells in response to the first clock signal; and
a second circuit configured to generate an internal clock signal indicative of an output timing of read data from an output terminal to an outside in response to the second clock signal.
6. The semiconductor device as claimed in claim 5 , wherein the first clock signal is different in a clock cycle period from the second clock signal.
7. The semiconductor device as claimed in claim 6 , wherein the first clock signal is longer in clock cycle period than the second clock signal.
8. The semiconductor device as claimed in claim 5 , wherein the oscillator circuit is configured to output the first clock signal to an output node thereof when the first command signal takes an active level, to output the second clock signal to the output node thereof when the second command signal takes an active level, and to fix a potential of the output node when both the first and second command signals take an inactive level, the first circuit being configured to perform the refresh operation on the memory cells when the first command signal takes the active level, the second circuit being configured to generate the internal clock signal when the second command signal takes the active level.
9. The semiconductor device as claimed in claim 5 , wherein the control circuit further includes a storage unit storing first code corresponding to a clock cycle period of the first clock signal and second code corresponding to a clock cycle period of the second clock signal.
10. The semiconductor device as claimed in claim 5 , wherein the second circuit comprises a clock generation circuit configured to receive an external clock signal and to delay the external clock signal to generate the internal clock signal.
11. The semiconductor device, as claimed in claim 5 , wherein the control circuit comprises a first input that receives the first control signal and a second input that receives the second control signal.