IP Library Granted Patent US 8,743,494
Granted Patent B2
US 8,743,494 · App. 13/330,144 · Granted Jun 3, 2014

Extended address mark

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Quick Facts
Patent No.
US 8,743,494
App. No.
13/330,144
Granted
Jun 3, 2014
Kind
B2
Abstract

An extended servo mark word is used when an error is detected from a servo mark. For example, a servo mark associated with a disk drive track may be detected during a data access operation. In response to an error in detecting the servo mark, at least one adjacent bit is evaluated together with the servo address mark to overcome the error.

Claims (29)

1. A method comprising:

reading data from an address mark;

detecting an error in the read address mark; and

when an error is detected from the read address mark, continuing to use the read data in combination with at least one adjacent bit to the read address mark to overcome the detected error, the at least one adjacent bit being part of either gray code or a preamble.

2. The method of claim 1 , wherein the at least one bit is directly adjacent to the address mark.

3. The method of claim 1 , wherein the error comprises a threshold number of erroneous bits occurring in any combination of the address mark and at least one adjacent bit to the address mark.

4. The method of claim 1 , further comprising:

reading a timestamp to verify the address mark; and

discarding the address mark if the timestamp falls outside a threshold value.

5. An apparatus comprising: a circuit configured to: detect an error in a servo address mark; and use an extended servo address mark word including the servo address mark and an adjacent bit from one of either a preamble or gray code, when an error is detected from a servo mark.

6. The apparatus of claim 5 , further comprising:

a disk having the servo address mark, preamble, and gray code.

7. The apparatus of claim 5 , wherein the circuit is further configured to overcome the error using the extended servo address mark.

8. The apparatus of claim 5 , wherein the error comprises a threshold number of erroneous bits occurring in any combination of the servo address mark and at least one adjacent bit to the servo address mark.

9. The apparatus of claim 5 , wherein the circuit is further configured to: read a timestamp to verify the servo address mark; and discard the servo mark if the timestamp falls outside a threshold value.

10. A method comprising:

during a data access operation, detecting a servo address mark associated with a disk drive track; and

in response to an error in detecting the servo address mark, evaluating at least one adjacent bit together with the servo address mark to overcome the error, wherein the at least one adjacent bit comprises part of one of a gray code and a preamble.

11. The method of claim 10 , further comprising:

reading a timestamp to verify the detected servo address mark; and

discarding the detected servo address mark if the timestamp falls outside a threshold value.

12. The method of claim 10 , wherein overcoming the error comprises overcoming a threshold number of erroneous bits in any combination of the servo address mark and the at least one adjacent bit.

13. The method of claim 1 , wherein a length of the read address mark is 9-bits long.

14. The method of claim 1 , wherein the detecting step comprises:

detecting an error when a single-bit error occurs.

15. The method of claim 1 , wherein the read address mark is the only address mark read to overcome the detected error.

16. The method of claim 10 , wherein the evaluating step includes evaluating two bits together with the servo address mark, wherein one of the two bits is part of the gray code and the other bit is part of the preamble.

17. The method of claim 10 , wherein the servo address mark is the only servo address mark evaluated to overcome the detected error.

18. The apparatus of claim 6 , wherein the bit is directly adjacent to the servo address mark.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2025
From: THE BANK OF NOVA SCOTIA
To: SEAGATE TECHNOLOGY US HOLDINGS, INC.; EVAULT, INC. (F/K/A I365 INC.); SEAGATE TECHNOLOGY LLC
Reel/Frame 070363/0903 →
RELEASE OF SECURITY INTEREST Recorded Jul 23, 2024
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: SEAGATE TECHNOLOGY LLC; EVAULT INC
Reel/Frame 068457/0076 →
RELEASE OF SECURITY INTEREST Recorded May 20, 2024
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: SEAGATE TECHNOLOGY LLC; EVAULT, INC. (F/K/A I365 INC.); SEAGATE TECHNOLOGY US HOLDINGS, INC.
Reel/Frame 067471/0955 →
SECURITY AGREEMENT Recorded Oct 15, 2012
From: SEAGATE TECHNOLOGY LLC; EVAULT, INC. (F/K/A I365 INC.); SEAGATE TECHNOLOGY US HOLDINGS, INC.
To: THE BANK OF NOVA SCOTIA, AS ADMINISTRATIVE AGENT
Reel/Frame 029127/0527 →
SECOND LIEN PATENT SECURITY AGREEMENT Recorded Oct 15, 2012
From: SEAGATE TECHNOLOGY LLC; EVAULT, INC. (F/K/A I365 INC.); SEAGATE TECHNOLOGY US HOLDINGS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 029253/0585 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 19, 2011
From: OZTURK, MUSTAFA CAN; POKHAREL, PUSKAL PRASSAD; VIKRAMADITYA, BARMESHWAR
To: SEAGATE TECHNOLOGY LLC
Reel/Frame 027411/0342 →