Startup circuit and input capacitor balancing circuit
View Patent ↗In one embodiment, an input capacitor balancing circuit for a power supply is provided. The circuit includes an input capacitance operable to filter input power for the power supply. The input capacitance has a first capacitor and a second capacitor coupled in series between an input voltage and a first node. A voltage divider circuit is coupled to the input voltage and operable to generate a divided voltage therefrom. A buffer circuit is operable to receive the divided voltage and, if the first capacitor and the second capacitor are not balanced, to provide current to the input capacitance to balance the first capacitor and the second capacitor.
1. A circuitry for a power supply, comprising:
a controller of the power supply, the controller having a startup circuit; and
a startup and input capacitor balancing circuit for the power supply, the startup and input capacitor balancing circuit comprising:
an input capacitance operable to filter input power for the power supply, the input capacitance having a first capacitor and a second capacitor coupled in series between an input voltage and a first node and configured to filter the input voltage;
a voltage divider circuit coupled to the input voltage and operable to generate a divided voltage therefrom; and
a buffer circuit operable to receive the divided voltage and, if the first capacitor and the second capacitor are not balanced, to provide current to the input capacitance to balance the first capacitor and the second capacitor, wherein the buffer circuit is operable to provide power for the startup circuit of the controller of the power supply.
2. The circuitry of claim 1 , wherein the buffer circuit comprises at least a first transistor and a second transistor, each transistor having a control terminal coupled to the voltage divider.
3. The circuitry of claim 2 , wherein the current provided by the buffer circuit is sourced through at least one of the first and the second transistors.
4. The circuitry of claim 2 , wherein the first and the second transistors of the buffer circuit are turned on and off by a difference in voltages associated with the divided voltage and a common connection of the first capacitor and a second capacitor of the input capacitance.
5. The circuitry of claim 1 , wherein the voltage divider circuit comprises at least a first resistor and a second resistor for dividing the input voltage.
6. The circuitry of claim 1 , wherein the buffer circuit is operable to drive the input capacitance through a third resistor.
7. The circuitry of claim 6 , wherein the third resistor is coupled at a second node between the first capacitor and a second capacitor.
8. A circuitry for a power supply, comprising:
a controller of the power supply, the controller having a startup circuit; and
a startup and input capacitor balancing circuit for the power supply, the startup and input capacitor balancing circuit comprising:
M input capacitors coupled in series between an input voltage providing input power for the power supply and a first node, the M input capacitors operable to filter the input voltage;
a voltage divider circuit coupled to the input voltage and operable to generate a plurality of divided voltages therefrom; and
M-1 buffer circuits each coupled to a respective common connection between respective two of the M input capacitors, each of the M-1 buffer circuits operable to receive a respective divided voltage from the voltage divider circuit and, if the respective two of the M input capacitors are not balanced, to provide current to balance the respective two of the M input capacitors, wherein at least one of the M-1 buffer circuits is operable to provide power for the startup circuit of the controller of the power supply.
9. The circuitry of claim 8 , wherein each of the buffer circuits comprises at least a first transistor and a second transistor, each of the first and second transistors having a control terminal coupled to the voltage divider.
10. The circuitry of claim 9 , wherein the current provided by each buffer circuit is sourced through at least one of the respective first and the second transistors.
11. The circuitry of claim 10 , wherein the first and the second transistors of each buffer circuit are turned on and off by a difference in voltages associated with the respective divided voltage and the respective common connection between the respective two of the M input capacitors.
12. The circuitry of claim 8 , wherein the voltage divider circuit comprises a plurality of resistors for dividing the input voltage.
13. The circuitry of claim 8 , wherein each buffer circuit is operable to drive the capacitance through a respective resistor coupled between the buffer circuit and the respective common connection.