Communication path latency measurement using capacitive coupling
View Patent ↗Systems and/or methods for measuring latency in an electronic device such as, e.g., a storage device, may include coupling circuitry configured to capacitively couple an outbound or write data path to an inbound or read data path. A latency measurement signal may be driven on the write data path, the coupling circuitry may transmit at least a portion of the latency measurement signal from the write data path to the read data path, and the latency measurement signal may be sensed on the read data path to be used to determine communication path latency in the device.
1. A system for measuring latency comprising:
a head configured to write and read data on a storage medium;
a controller configured to write and read data using the head;
a write data path electrically coupling the controller to the head for transmission of write data signals;
a read data path electrically coupling the controller to the head for transmission of read data signals; and
coupling circuitry configured to capacitively couple the write data path and the read data path,
the controller configured to determine a latency of a communication path comprising at least a portion of each of the write data path and the read data path using at least a latency measurement signal driven on the write data path.
2. The system of claim 1 , wherein the head is further configured to operate in at least one of a bit-patterned media system or a heat-assisted magnetic recording system.
3. The system of claim 1 , wherein the coupling circuitry is located in the head.
4. The system of claim 3 , wherein the coupling circuitry comprises a resistor configured to behave as a bias-shunt resistor to decrease resistance of a read transducer of the head during reading of data from the storage medium using the read transducer.
5. The system of claim 1 , wherein the controller is configured to set a read transducer bias of the read data path to zero when driving a latency measurement signal on the write data path.
6. The system of claim 1 , wherein the coupling circuitry comprises a capacitor and a resistor configured to reduce interference components from reflections and local couplings when a latency measurement signal is driven on the write data path.
7. The system of claim 1 , wherein the system further comprises a preamplifier located between the controller and the head, wherein the preamplifier is configured to amplify the write data signals transmitted along the write data path and the read data signals transmitted along the read data path, and wherein the coupling circuitry is located in the preamplifier.
8. The system of claim 7 , wherein the coupling circuitry comprises a capacitor and a switch, the switch configured to selectively couple the capacitor to the write data path when a latency measurement signal is driven on one of the write data path and the read data path.
9. A system comprising:
a controller configured to write and read data on a storage medium using a plurality of heads;
a preamplifier located between the controller and the plurality of heads, wherein the preamplifier is configured to amplify the write data signals transmitted from the controller to the plurality of heads and the read data signals transmitted from the plurality of heads to the controller,
a common write data path electrically coupling the controller to the preamplifier for transmission of write data signals from the controller to the preamplifier;
a common read data path electrically coupling the controller to the preamplifier for transmission of read data signals from the preamplifier to the controller; and
coupling circuitry located in the preamplifier configured to capacitively couple the common write data path to the common read data path,
the controller configured to determine a latency of a communication path comprising at least each of the common write data path and the common read data path using at least the latency measurement signal driven on the common write data path.
10. The system of claim 9 , wherein the preamplifier further comprises multiplexing circuitry configured to selectively electrically couple the common write data path to a write data path of one of the plurality of heads and the common read data path to a read data path of one of the plurality of heads, wherein the coupling circuitry is configured to capacitively couple the write data path and the read data path for each head of the plurality of heads.
11. The system of claim 9 , wherein the preamplifier further comprises multiplexing circuitry configured to selectively electrically couple the common write data path to a write data path of one of the plurality of heads and the common read data path to a read data path of one of the plurality of heads, wherein the controller is further configured to selectively electrically couple the coupling circuitry to the common write data path and the common read data path.
12. A method for use in measuring latency in an electronic device including a write data path for the transmission of write data signals and a read data path for the transmission of read data signals extending between a controller and a head, the method comprising:
providing coupling circuitry configured to capacitively couple a write data path to a read data path when a latency measurement signal is driven on the write data path;
driving a latency measurement signal on the write data path;
sensing the latency measurement signal on the read data path; and
determining the latency of a communication path comprising at least a portion of each of the write data path and read data path using at least the sensed latency measurement signal.
13. The method of claim 12 , wherein driving a latency measurement signal on the write data path comprises transmitting a square wave on the write data path.
14. The method of claim 12 , wherein determining the latency of a communication path comprises comparing the sensed latency measurement signal to a reference signal.
15. The method of claim 14 , wherein comparing the sensed latency measurement signal to a reference signal comprises comparing the zero crossings of the sensed latency measurement signal and the reference signal.
16. The method of claim 12 , wherein a preamplifier is located between the controller and the head, wherein preamplifier is configured to amplify write data signals transmitted along the write data path and read data signals transmitted along the read data path, and wherein the coupling circuitry is located in the preamplifier.
17. The method of claim 12 , wherein the coupling circuitry is configured to filter low frequency components from being transmitted between the write data path and the read data path.