IP Library Granted Patent US 8,385,668
Granted Patent B2
US 8,385,668 · App. 13/363,308 · Granted Feb 26, 2013

Image processing circuit, and display panel driver and display device mounting the circuit

Inventors: Hirobumi Furihata (Kanagawa, JP); Takashi Nose (Kanagawa, JP)
Assignee: Renesas Electronics Corporation
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Quick Facts
Patent No.
US 8,385,668
App. No.
13/363,308
Granted
Feb 26, 2013
Kind
B2
Abstract

A display panel driver includes a compression circuit configured to, when receiving image data of a plurality of pixels of a target block, generate compressed image data corresponding to the target block by compressing the image data, an image memory configured to store the compressed image data, a decompression circuit configured to generate decompressed image data by decompressing the compressed image data reading from the image memory, and a drive circuit configured to drive a display panel in response to the decompressed image data. The number of bits of the compression type recognition bit of the compressed image data becomes low, when the correlation between the image data of the plurality of pixels becomes low.

Claims (27)

1. A display panel driver comprising:

a compression circuit configured to, when receiving image data of a plurality of pixels of a target block, generate compressed image data corresponding to said target block by compressing said image data;

an image memory configured to store said compressed image data;

a decompression circuit configured to generate decompressed image data by decompressing said compressed image data reading from said image memory; and

a drive circuit configured to drive a display panel in response to said decompressed image data,

wherein said compression circuit selects one of a plurality of compression methods based on a correlation between said image data of said plurality of pixels of said target block, and generates said compressed image data by using said selected compression method,

wherein the number of bits of said compressed image data is constant regardless of said plurality of compression methods,

wherein said compressed image data includes a compression type recognition bit indicating a type of said selected compression method, and

wherein the number of bits of said compression type recognition bit of said compressed image data becomes low, when said correlation between said image data of said plurality of pixels becomes low.

2. A display device comprising:

a display panel; and

a display panel driver configured to drive said display panel,

wherein said display panel driver includes:

a compression circuit configured to, when receiving image data of a plurality of pixels of a target block, generate compressed image data corresponding to said target block by compressing said image data,

an image memory configured to store said compressed image data,

a decompression circuit configured to generate decompressed image data by decompressing said compressed image data reading from said image memory, and

a drive circuit configured to drive a display panel in response to said decompressed image data,

wherein said compression circuit selects one of a plurality of compression methods based on a correlation between said image data of said plurality of pixels of said target block, and generates said compressed image data by using said selected compression method,

wherein the number of bits of said compressed image data is constant regardless of said plurality of compression methods,

wherein said compressed image data includes a compression type recognition bit indicating a type of said selected compression method, and

wherein the number of bits of said compression type recognition bit of said compressed image data becomes low, when said correlation between said image data of said plurality of pixels becomes low.

3. An image processing circuit comprising:

a compression circuit configured to, when receiving image data of a plurality of pixels of a target block, generate compressed image data corresponding to said target block by compressing said image data,

wherein said compression circuit selects one of a plurality of compression methods based on a correlation between said image data of said plurality of pixels of said target block, and generates said compressed image data by using said selected compression method,

wherein the number of bits of said compressed image data is constant regardless of said plurality of compression methods,

wherein said compressed image data includes a compression type recognition bit indicating a type of said selected compression method, and

wherein the number of bits of said compression type recognition bit of said compressed image data becomes low, when said correlation between said image data of said plurality of pixels becomes low.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2024
From: SYNAPTICS JAPAN GK
To: SYNAPTICS INCORPORATED
Reel/Frame 067793/0211 →
SECURITY INTEREST Recorded Sep 27, 2017
From: SYNAPTICS INCORPORATED
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 044037/0896 →
CHANGE OF NAME Recorded Aug 8, 2016
From: SYNAPTICS DISPLAY DEVICES GK
To: SYNAPTICS JAPAN GK
Reel/Frame 039711/0862 →
CHANGE OF NAME Recorded May 29, 2015
From: RENESAS SP DRIVERS INC.
To: SYNAPTICS DISPLAY DEVICES KK
Reel/Frame 035796/0947 →
CHANGE OF NAME Recorded May 29, 2015
From: SYNAPTICS DISPLAY DEVICES KK
To: SYNAPTICS DISPLAY DEVICES GK
Reel/Frame 035797/0036 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 19, 2014
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS SP DRIVERS INC.
Reel/Frame 033778/0137 →
Priority Claims (1)
JP 2008-171364 · Jun 30, 2008 · national
Continuity (3)
Continuation 13064037 · Mar 2, 2011
Continuation 12457941 · Jun 25, 2009
Related Publication 20120127188A1 · May 24, 2012