Granted Patent B2

US 8,904,255 · App. 13/401,030 · Granted Dec 2, 2014

Abstract

Claims (77)

1. An integrated circuit comprising:

scan test circuitry comprising at least one scan chain having a plurality of scan cells;

additional circuitry subject to testing utilizing the scan test circuitry; and

a clock distribution network configured to provide a plurality of clock signals to respective portions of the integrated circuit;

the clock distribution network comprising:

clock gating circuitry configured to control delivery of one or more of the clock signals along respective clock signal lines of the clock distribution network at least in part responsive to a scan shift control signal and a functional enable signal;

wherein the scan shift control signal is also utilized to cause the scan cells of the scan chain to form a serial shift register during scan testing; and

wherein the clock gating circuitry is configured to control delivery of the clock signals along the respective clock signal lines of the clock distribution network utilizing controllable clock gating latches serially inserted in each line in a manner that permits determination of whether a particular clock delay defect on one of the clock signal lines that causes a scan error during scan testing will also cause a functional error during functional operation.

2. The integrated circuit of claim 1 wherein the scan cells of the scan chain form the serial shift register responsive to the scan shift control signal being at a first designated logic level and the scan cells capture functional data when the scan shift control signal is at a second designated logic level.

3. The integrated circuit of claim 1 wherein the clock gating circuitry further comprises for each of at least a subset of the clock signal lines of the clock distribution network:

a clock gating latch coupled in series with the clock signal line of the clock distribution network; and

logic circuitry having an output coupled to a first control input of the clock gating latch and being operative to control a state of the clock gating latch at least in part responsive to the scan shift control signal.

4. A processing device comprising the integrated circuit of claim 1 .

5. The integrated circuit of claim 1 wherein the clock gating circuitry further comprises:

a clock gating latch having first and second control inputs; and

logic circuitry having an output coupled to the first control input of the clock gating latch, and an input configured to receive the scan shift control signal; and

wherein the second control input of the clock gating latch is configured to receive the functional enable signal.

6. The integrated circuit of claim 5 wherein the logic circuitry has an additional input configured to receive a test data signal.

7. An integrated circuit comprising:

scan test circuitry comprising at least one scan chain having a plurality of scan cells;

additional circuitry subject to testing utilizing the scan test circuitry; and

a clock distribution network configured to provide a plurality of clock signals to respective portions of the integrated circuit;

the clock distribution network comprising:

clock gating circuitry configured to control delivery of one or more of the clock signals along respective clock signal lines of the clock distribution network at least in part responsive to a scan shift control signal and a functional enable signal;

wherein the scan shift control signal is also utilized to cause the scan cells of the scan chain to form a serial shift register during scan testing;

wherein the clock gating circuitry comprises for each of at least a subset of the clock signal lines of the clock distribution network:

a clock gating latch coupled in series with the clock signal line of the clock distribution network; and

logic circuitry having an output coupled to a first control input of the clock gating latch and being operative to control a state of the clock gating latch at least in part responsive to the scan shift control signal; and

wherein the clock gating latch further comprises a second control input operative to control a state of the clock gating latch at least in part responsive to the functional enable signal, wherein the functional enable signal is at a first designated logic level during scan testing and at a second designated logic level outside of scan testing.

8. An integrated circuit comprising:

scan test circuitry comprising at least one scan chain having a plurality of scan cells;

additional circuitry subject to testing utilizing the scan test circuitry; and

a clock distribution network configured to provide a plurality of clock signals to respective portions of the integrated circuit;

the clock distribution network comprising:

clock gating circuitry configured to control delivery of one or more of the clock signals along respective clock signal lines of the clock distribution network at least in part responsive to a scan shift control signal and a functional enable signal;

wherein the scan shift control signal is also utilized to cause the scan cells of the scan chain to form a serial shift register during scan testing;

wherein the clock gating circuitry comprises for each of at least a subset of the clock signal lines of the clock distribution network:

a clock gating latch coupled in series with the clock signal line of the clock distribution network; and

logic circuitry having an output coupled to a first control input of the clock gating latch and being operative to control a state of the clock gating latch at least in part responsive to the scan shift control signal; and

wherein the logic circuitry comprises a logic gate having a first input configured to receive the scan shift control signal and a second input configured to receive a test data signal.

9. The integrated circuit of claim 8 wherein the test data signal comprises a particular bit of a programmable test data register.

10. The integrated circuit of claim 9 wherein the programmable test data register comprises a separate bit for each of a plurality of clock gating latches of the clock gating circuitry.

11. The integrated circuit of claim 8 wherein the test data signal comprises a chip-level primary input signal.

12. The integrated circuit of claim 8 wherein the logic circuitry comprises a two-input OR gate.

13. An integrated circuit comprising:

scan test circuitry comprising at least one scan chain having a plurality of scan cells;

additional circuitry subject to testing utilizing the scan test circuitry; and

a clock distribution network configured to provide a plurality of clock signals to respective portions of the integrated circuit;

the clock distribution network comprising:

clock gating circuitry configured to control delivery of one or more of the clock signals along respective clock signal lines of the clock distribution network at least in part responsive to a scan shift control signal and a functional enable signal;

wherein the scan shift control signal is also utilized to cause the scan cells of the scan chain to form a serial shift register during scan testing;

wherein the clock gating circuitry comprises for each of at least a subset of the clock signal lines of the clock distribution network:

a clock gating latch coupled in series with the clock signal line of the clock distribution network; and

logic circuitry having an output coupled to a first control input of the clock gating latch and being operative to control a state of the clock gating latch at least in part responsive to the scan shift control signal;

wherein the clock gating latch comprises a clock signal input and an output;

wherein the clock gating latch is controllable between an active state in which a clock signal applied to its clock signal input passes to its output and a freeze state in which the clock signal applied to its clock signal input does not pass to its output but the output is instead maintained at a designated logic level; and

wherein the clock gating latch is placed in its active state responsive to the functional enable signal being at a designated logic level or responsive to one of the scan shift control signal and a test data signal being at the designated logic level, and is otherwise in its freeze state.

14. A method comprising:

utilizing a scan shift control signal to cause scan cells of a scan chain in an integrated circuit to form a serial shift register during scan testing; and

controlling delivery of clock signals along respective clock signal lines of a clock distribution network of the integrated circuit at least in part responsive to the scan shift control signal and a functional enable signal;

wherein the controlling step comprises controlling delivery of the clock signals along the respective clock signal lines of the clock distribution network utilizing controllable clock gating latches serially inserted in each line in a manner that permits determination of whether a particular clock delay defect on one of the clock signal lines that causes a scan error during scan testing will also cause a functional error during functional operation.

15. A non-transitory computer-readable storage medium having computer program code embodied therein for use in scan testing an integrated circuit, wherein the computer program code when executed in a testing system causes the testing system to perform the steps of the method of claim 14 .

16. An apparatus comprising:

clock gating circuitry comprising a plurality of clock gating latches configured for serial insertion into respective clock signal lines of a clock distribution network of an integrated circuit;

wherein the clock gating latches are configured to control delivery of clock signals along respective ones of the clock signal lines at least in part responsive to a scan shift control signal and a functional enable signal;

wherein the scan shift control signal is also utilized to cause scan cells of a scan chain of the integrated circuit to form a serial shift register during scan testing; and

wherein the clock gating latches comprise respective controllable clock gating latches serially inserted in each line in a manner that permits determination of whether a particular clock delay defect on one of the clock signal lines that causes a scan error during scan testing will also cause a functional error during functional operation.

17. The apparatus of claim 16 wherein the clock gating circuitry further comprises for each of at least a subset of the clock signal lines of the clock distribution network, in addition to a given one of the clock gating latches being coupled in series with the clock signal line of the clock distribution network, logic circuitry having an output coupled to a first control input of the given clock gating latch and operative to control a state of the given clock gating latch at least in part responsive to the scan shift control signal.

18. The apparatus of claim 17 wherein the given clock gating latch further comprises a clock signal input and an output, and wherein the given clock gating latch is controllable between an active state in which a clock signal applied to its clock signal input passes to its output and a freeze state in which the clock signal applied to its clock signal input does not pass to its output but the output is instead maintained at a designated logic level.

19. A processing system comprising:

a processor; and

a memory coupled to the processor and configured to store information characterizing an integrated circuit design;

wherein the processing system is configured to provide scan test circuitry and a clock distribution network within the integrated circuit design, the scan test circuitry comprising at least one scan chain having a plurality of scan cells, the clock distribution network being configured to provide a plurality of clock signals to respective portions of the scan test circuitry;

the clock distribution network comprising:

clock gating circuitry configured to control delivery of one or more of the clock signals along respective clock signal lines of the clock distribution network at least in part responsive to a scan shift control signal and a functional enable signal;

wherein the scan shift control signal also causes the scan cells of the scan chain to form a serial shift register during scan testing; and

wherein the clock gating circuitry is configured to control delivery of the clock signals along the respective clock signal lines of the clock distribution network utilizing controllable clock gating latches serially inserted in each line in a manner that permits determination of whether a particular clock delay defect on one of the clock signal lines that causes a scan error during scan testing will also cause a functional error during functional operation.

Assignments (8)