Methods and apparatus for reusing snoop responses and data phase results in a cache controller
View Patent ↗Methods and apparatus are provided for reusing snoop responses and data phase results in a cache controller. A cache controller receives a broadcast combined snoop response from a bus controller, wherein the broadcast combined snoop response corresponds to an incoming bus transaction BTR1 corresponding to a cache transaction CTR1 for an entry in at least one cache and wherein the combined snoop response is a combination of at least one snoop response from a plurality of cache controllers; receives broadcast cache line data from a source cache as instructed by the bus controller for the entry during a data phase; and processes a subsequent cache transaction CTR2 for the entry based on one or more of the broadcast combined snoop response and the broadcast cache line data.
1. A method, comprising:
receiving a broadcast combined snoop response and at least one sideband signal from a bus controller, wherein said broadcast combined snoop response corresponds to an incoming bus transaction BTR1 corresponding to a cache transaction CTR1 for an entry in at least one cache and wherein said combined snoop response is a combination of at least one snoop response from a plurality of cache controllers, wherein said bus controller broadcasts said broadcast combined snoop response to a plurality of cache controllers, wherein said at least one sideband signal indicates one or more of a status and a phase of bus transaction merging performed by said bus controller;
receiving broadcast cache line data from a source cache as instructed by said bus controller for said entry during a data phase, wherein said source cache broadcasts said broadcast cache line data to a plurality of peer cache controllers with at least one additional sideband signal; and
processing a subsequent cache transaction CTR2 for said entry based on one or more of said broadcast combined snoop response and said broadcast cache line data by using at least one of said sideband signals to align with merged bus transaction phases of said incoming bus transaction BTR1 and said subsequent cache transaction CTR2 to implement said bus transaction merging.
2. The method of claim 1 , wherein said subsequent cache transaction CTR2 for said entry is processed in a bus controller based on a common snoop request phase of said bus transaction BTR1.
3. The method of claim 1 , wherein said subsequent cache transaction CTR2 for said entry is processed in a bus controller based on a current phase of said bus transaction BTR1.
4. The method of claim 2 , wherein a bus controller performs a common data phase for bus transactions BTR1 and BTR2 associated with said incoming cache transaction CTR1 and said subsequent cache transaction CTR2, respectively.
5. The method of claim 1 , wherein said source cache is requested during said data phase to source data for said incoming bus transaction.
6. The method of claim 1 , further comprising the step of waiting for said broadcast snoop response followed by waiting for cache line data in a data phase response.
7. The method of claim 1 , further comprising the step of waiting for said broadcast cache line data.
8. The method of claim 1 , wherein said broadcast cache line data is used if said subsequent cache transaction for said entry comprises a read operation.
9. The method of claim 3 , wherein said current phase is an address phase and wherein said broadcast cache line data is used if said corresponding cache transactions CTR1 and CTR2 are both not write operations.
10. The method of claim 3 , wherein said current phase is a snoop response phase and wherein said broadcast cache line data is used if said corresponding cache transactions CTR1 and CTR2 are both not write operations.
11. The method of claim 3 , wherein said current phase is a data phase and wherein said broadcast cache line data is used if said corresponding cache transactions CTR1 and CTR2 are both not write operations.
12. The method of claim 3 , wherein said current phase is one or more of a data phase and a response phase and further comprising the step of invalidating said entry in said source cache if said subsequent bus transaction for said entry comprises a write operation and said incoming cache transaction CTR1 is a read operation.
13. The method of claim 1 , further comprising the step of receiving an indicator to make use of said cache line data but not to allocate a cache entry when one of the bus transactions is a Write operation.
14. The method of claim 1 , further comprising the step of receiving an indicator to invalidate said cache line data in the source cache if one of the bus transactions corresponding to this cache line is a write operation.
15. The method of claim 1 , further comprising the step of receiving an indicator that indicates that said broadcast combined snoop response corresponds to a write operation to inform other caches among the plurality of cache controllers to make use of the subsequent data phase only if those cache controllers have a processor read without performing any allocation.
16. The method of claim 1 , further comprising the step of receiving an indicator that indicates that said broadcast cache line data corresponds to a write operation to inform other caches among the plurality of cache controllers to make use of the data phase only if those cache controllers have a processor read without performing any allocation.
17. A cache controller, comprising:
a memory; and
at least one hardware device, coupled to the memory, configured to:
receive a broadcast combined snoop response and at least one sideband signal from a bus controller, wherein said broadcast combined snoop response corresponds to an incoming bus transaction BTR1 corresponding to a cache transaction CTR1 for an entry in at least one cache and wherein said combined snoop response is a combination of at least one snoop response from a plurality of cache controllers, wherein said bus controller broadcasts said broadcast combined snoop response to a plurality of cache controllers, wherein said at least one sideband signal indicates one or more of a status and a phase of bus transaction merging performed by said bus controller;
receive broadcast cache line data from a source cache as instructed by said bus controller for said entry during a data phase, wherein said source cache broadcasts said broadcast cache line data to a plurality of peer cache controllers with at least one additional sideband signal; and
process a subsequent cache transaction CTR2 for said entry based on one or more of said broadcast combined snoop response and said broadcast cache line data by using at least one of said sideband signals to align with merged bus transaction phases of said incoming bus transaction BTR1 and said subsequent cache transaction CTR2 to implement said bus transaction merging.
18. The cache controller of claim 17 , wherein said subsequent cache transaction CTR2 for said entry is processed in a bus controller based on a common snoop request phase of said bus transaction BTR1.
19. The cache controller of claim 17 , wherein said subsequent cache transaction CTR2 for said entry is processed in a bus controller based on a current phase of said bus transaction BTR1.
20. The cache controller of claim 18 , wherein a bus controller performs a common data phase for bus transactions BTR1 and BTR2 associated with said incoming cache transaction CTR1 and said subsequent cache transaction CTR2, respectively.
21. The cache controller of claim 17 , wherein said source cache is requested during said data phase to source data for said incoming bus transaction.
22. The cache controller of claim 17 , wherein said at least one hardware device is further configured to wait for said broadcast snoop response followed by waiting for cache line data in a data phase response.
23. The cache controller of claim 17 , wherein said at least one hardware device is further configured to wait for said broadcast cache line data.
24. The cache controller of claim 17 , wherein said broadcast cache line data is used if said subsequent cache transaction for said entry comprises a read operation.
25. The cache controller of claim 19 , wherein said current phase is an address phase and wherein said broadcast cache line data is used if said corresponding cache transactions CTR1 and CTR2 are both not write operations.
26. The cache controller of claim 19 , wherein said current phase is a snoop response phase and wherein said broadcast cache line data is used if said corresponding cache transactions CTR1 and CTR2 are both not write operations.
27. The cache controller of claim 19 , wherein said current phase is a data phase and wherein said broadcast cache line data is used if said corresponding cache transactions CTR1 and CTR2 are both not write operations.
28. The cache controller of claim 19 , wherein said current phase is one or more of a data phase and a response phase and wherein said at least one hardware device is further configured to invalidate said entry in said source cache if said subsequent bus transaction for said entry comprises a write operation and said incoming cache transaction CTR1 is a read operation.
29. The cache controller of claim 17 , wherein said at least one hardware device is further configured to receive an indicator to make use of said cache line data but not to allocate a cache entry when one of the bus transactions is a write operation.
30. The cache controller of claim 17 , wherein said at least one hardware device is further configured to receive an indicator to invalidate said cache line data in the source cache if one of the bus transactions corresponding to this cache line is a write operation.
31. The cache controller of claim 17 , wherein said at least one hardware device is further configured to receive an indicator that indicates that said broadcast combined snoop response corresponds to a write operation to inform other caches among the plurality of cache controllers to make use of the subsequent data phase only if those cache controllers have a processor read without performing any allocation.
32. The cache controller of claim 17 , wherein said at least one hardware device is further configured to receive an indicator that indicates that said broadcast cache line data corresponds to a write operation to inform other caches among the plurality of cache controllers to make use of the data phase only if those cache controllers have a processor read without performing any allocation.
33. The cache controller of claim 17 , wherein said at least one hardware device is one or more of an integrated circuit, a digital signal processor, a microprocessor, a micro-controller, and a general-purpose computer.
34. The cache controller of claim 17 , wherein said cache controller is embodied on an integrated circuit.
35. An article of manufacture, comprising a tangible machine readable recordable medium containing one or more programs which when executed implement the steps of:
receiving a broadcast combined snoop response and at least one sideband signal from a bus controller, wherein said broadcast combined snoop response corresponds to an incoming bus transaction BTR1 corresponding to a cache transaction CTR1 for an entry in at least one cache and wherein said combined snoop response is a combination of at least one snoop response from a plurality of cache controllers, wherein said bus controller broadcasts said broadcast combined snoop response to a plurality of cache controllers, wherein said at least one sideband signal indicates one or more of a status and a phase of bus transaction merging performed by said bus controller;
receiving broadcast cache line data from a source cache as instructed by said bus controller for said entry during a data phase, wherein said source cache broadcasts said broadcast cache line data to a plurality of peer cache controllers with at least one additional sideband signal; and
processing a subsequent cache transaction CTR2 for said entry based on one or more of said broadcast combined snoop response and said broadcast cache line data by using at least one of said sideband signals to align with merged bus transaction phases of said incoming bus transaction BTR1 and said subsequent cache transaction CTR2 to implement said bus transaction merging.
36. An integrated circuit, comprising:
receiver circuitry configured to:
receive a broadcast combined snoop response and at least one sideband signal from a bus controller, wherein said broadcast combined snoop response corresponds to an incoming bus transaction BTR1 corresponding to a cache transaction CTR1 for an entry in at least one cache and wherein said combined snoop response is a combination of at least one snoop response from a plurality of cache controllers, wherein said bus controller broadcasts said broadcast combined snoop response to a plurality of cache controllers, wherein said at least one sideband signal indicates one or more of a status and a phase of bus transaction merging performed by said bus controller;
receive broadcast cache line data from a source cache as instructed by said bus controller for said entry during a data phase, wherein said source cache broadcasts said broadcast cache line data to a plurality of peer cache controllers with at least one additional sideband signal; and
cache controller circuitry configured to:
process a subsequent cache transaction CTR2 for said entry based on one or more of said broadcast combined snoop response and said broadcast cache line data by using at least one of said sideband signals to align with merged bus transaction phases of said incoming bus transaction BTR1 and said subsequent cache transaction CTR2 to implement said bus transaction merging.