Organic interface substrate having interposer with through-semiconductor vias
View Patent ↗An interface substrate is disclosed which includes an interposer having through-semiconductor vias. An upper and a lower organic substrate are further built around the interposer. The disclosed interface substrate enables the continued use of low cost and widely deployed organic substrates for semiconductor packages while providing several advantages. The separation of the organic substrate into upper and lower substrates enables the cost effective matching of fabrication equipment. By providing an opening in one of the organic substrates, one or more semiconductor dies may be attached to exposed interconnect pads coupled to through-semiconductor vias of the interposer, enabling the use of flip chips with high-density microbump arrays and the accommodation of dies with varied bump pitches. By providing the opening specifically in the upper organic substrate, a package-on-package structure with optimized height may also be provided.
1. An interface substrate comprising:
an interposer having a first plurality of through-semiconductor vias (TSVs) for electrically connecting a first plurality of lower interconnect pads situated on a lower organic substrate to a first plurality of upper interconnect pads situated on an upper organic substrate;
a second plurality of lower interconnect pads in said lower organic substrate being utilized as lower contact pads for receiving a lower semiconductor die, said lower contact pads being capable of connection to a second plurality of said upper interconnect pads;
said upper organic substrate having upper contact pads for receiving an upper semiconductor die, said upper contact pads being capable of connection to said first and second plurality of upper interconnect pads.
2. The interface substrate of claim 1 , wherein said interposer comprises silicon.
3. The interface substrate of claim 2 , wherein said first plurality of TSVs are through-silicon vias.
4. The interface substrate of claim 1 , wherein a pitch of said second plurality of lower interconnect pads is less than a pitch of said upper contact pads.
5. A semiconductor package comprising:
an interposer having a first plurality of through-semiconductor vias (TSVs) for electrically connecting a first plurality of lower interconnect pads situated on a lower organic substrate to a first plurality of upper interconnect pads situated on an upper organic substrate;
a second plurality of lower interconnect pads in said lower organic substrate being utilized as lower contact pads receiving a lower semiconductor die, said lower contact pads being capable of connection to a second plurality of said upper interconnect pads;
said upper organic substrate having upper contact pads receiving an upper semiconductor die, said upper contact pads being capable of connection to said first and second plurality of upper interconnect pads.
6. The semiconductor package of claim 5 , wherein said interposer comprises silicon.
7. The semiconductor package of claim 6 , wherein said first plurality of TSVs are through-silicon vias.
8. The semiconductor package of claim 5 , wherein a pitch of said second plurality of lower interconnect pads is less than a pitch of said upper contact pads.
9. The semiconductor package of claim 5 , wherein a minimum pad pitch of said upper organic substrate is less than a minimum pad pitch of said lower organic substrate.
10. The semiconductor package of claim 5 , wherein said upper semiconductor die is a flip-chip.
11. The semiconductor package of claim 5 , wherein said lower semiconductor die is a flip-chip.
12. The semiconductor package of claim 5 , wherein each of said upper organic substrate and said lower organic substrate comprises multiple conductor layers.
13. The semiconductor package of claim 5 , further comprising a plurality of solder balls connected to said lower organic substrate and to said lower semiconductor die.