IP Library Granted Patent US 8,421,829
Granted Patent B2
US 8,421,829 · App. 13/405,999 · Granted Apr 16, 2013

Liquid crystal display controller

Inventors: Yasuyuki Kudo (Kamakura, JP); Tsutomu Furuhashi (Yokohama, JP); Yoshikazu Yokota (Kodaira, JP); Toshimitsu Matsudo (Shinagawa, JP); Atsuhiro Higa (Yokohama, JP)
Assignee: Renesas Electronics Corporation
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Quick Facts
Patent No.
US 8,421,829
App. No.
13/405,999
Granted
Apr 16, 2013
Kind
B2
Abstract

The present invention provides a liquid crystal display controller device and method which provides for a full and/or partial display with good display quality and/or low power consumption based on the scanning period for an active scan line being dependent upon a number of reference clock pulses. Some embodiments of the present invention include one or more of the following features: keeping the frequency substantially constant for different numbers of active scan lines, allowing change of the frequency due to characteristics of the LCD, displaying gradation with near linear effective voltage characteristics, displaying graduation data with lower power, or displaying a partial or full screen in a mobile device, for example, a cell phone.

Claims (23)

1. A device for controlling a display panel on which a plurality of data lines and a plurality of scanning lines are arranged in a matrix, the device comprising:

a first generator for generating an original clock signal;

a memory for storing display data received from an external device;

a gradation processor to receive the display data from the memory;

a first register for setting a division ratio of the original clock signal and a number of active lines of the display panel, all of which being received from the external device;

a second register for setting a gradation palette data, and for reading the display data, to convert the display data into a PWM signal for each of red, green and blue data with the gradation processor;

a second generator for dividing the original clock signal by the division ratio to generate a reference clock, to thereby generate a line pulse synchronized with the scanning period and a frame pulse synchronized with a frame period; and

a data line driver for reading out the PWM signal from the gradation processor, for converting the PWM signal into a driving voltage to be provided to the display panel,

wherein the gradation processor reads out the display data line by line from an address on the memory according to the line pulse, the address corresponding to a top line of the display panel, and repeats the readout of the display data by using the address corresponding to the top line of the display panel according to the frame pulse.

2. The device according to claim 1 ,

wherein the second generator generates the line pulse and the frame pulse from the reference clock based on the number of clock of the reference clock signal per the scanning period and the number of the active lines of the display panel.

3. The device according to claim 1 ,

wherein a frame frequency of the frame pulse is determined from the division ratio of the original clock signal, the number of clock of the reference clock signal per scanning period, and the number of the active lines of the display panel.

4. The device according to the claim 1 ,

wherein the frame frequency of the frame pulse is adjustable by at least one of the division ratio of the original clock signal, the number of clock of the reference clock signal per scanning period, and the number of the active lines of the display panel to be set in the register from the external device.

5. The device according to the claim 1 ,

wherein the number of clock of the reference clock signal per scanning period is an integer.

6. The device according to claim 1 ,

wherein the device can operate in a partial display mode or low power consumption mode of the display panel.

7. The device according to claim 1 ,

wherein the device is incorporated into a cellular phone system.

8. The device according to the claim 1 , the device further comprising a scanning line driver for outputting a selecting voltage and a non-selecting voltage to the scanning lines on the display panel.

9. The device according to claim 8 , the device is one LSI chip.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2024
From: SYNAPTICS JAPAN GK
To: SYNAPTICS INCORPORATED
Reel/Frame 067793/0211 →
SECURITY INTEREST Recorded Sep 27, 2017
From: SYNAPTICS INCORPORATED
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 044037/0896 →
CHANGE OF NAME Recorded Aug 8, 2016
From: SYNAPTICS DISPLAY DEVICES GK
To: SYNAPTICS JAPAN GK
Reel/Frame 039711/0862 →
CHANGE OF NAME Recorded May 29, 2015
From: RENESAS SP DRIVERS INC.
To: SYNAPTICS DISPLAY DEVICES KK
Reel/Frame 035796/0947 →
CHANGE OF NAME Recorded May 29, 2015
From: SYNAPTICS DISPLAY DEVICES KK
To: SYNAPTICS DISPLAY DEVICES GK
Reel/Frame 035797/0036 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 19, 2014
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS SP DRIVERS INC.
Reel/Frame 033778/0137 →
Priority Claims (2)
JP 2000-231351 · Jul 26, 2000 · national
JP 2000-309300 · Oct 4, 2000 · national
Continuity (4)
Continuation 12250305 · Oct 13, 2008
Continuation 11172563 · Jun 29, 2005
Continuation 09891677 · Jun 25, 2001
Related Publication 20120154465A1 · Jun 21, 2012