IP Library Granted Patent US 8,937,797
Granted Patent B2
US 8,937,797 · App. 13/423,891 · Granted Jan 20, 2015

Method and apparatus to detect a broken wire condition in an integrated circuit

Inventors: Franco Noel Martin Pirchio (Ciudad de Buenos Aires, AR); Cory Voisine (Weare, NH); Hernan D. Romero (Pcia. Buenos Aires, AR); Gerardo Monreal (Pilar, AR)
Assignee: Allegro Microsystems, LLC
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Quick Facts
Patent No.
US 8,937,797
App. No.
13/423,891
Granted
Jan 20, 2015
Kind
B2
Abstract

An integrated circuit includes circuitry to sense the occurrence of a break in a ground connection and/or supply connection and to indicate same to an exterior environment. In at least one implementation, the break may be indicated by providing a signal on an output terminal of the device that is not associated with a normal output of the device.

Claims (47)

1. An integrated circuit comprising:

a supply terminal to connect to an external power supply;

a ground terminal to connect to an external ground;

an output terminal to connect to an external load;

an output amplifier coupled to the output terminal to generate an output signal on the output terminal during normal device operation; and

circuitry to prevent current from flowing through the output terminal if at least one of the following occurs during device operation: a connection between the ground terminal and the external ground is broken and a connection between the supply terminal and the external power supply is broken;

wherein the external load is an external pull-down load, the output amplifier includes an output stage having a p-channel transistor and an n-channel transistor; and the circuitry to prevent current from flowing through the output terminal includes:

a first switch coupled between the n-channel transistor and the ground terminal; and

a control circuit to detect a break in a connection between the ground terminal and the external ground and to turn off the first switch in response thereto, wherein the control circuit comprises a second switch connected between the output terminal of the integrated circuit and an input terminal of the first switch, the second switch to turn on if a break occurs in a connection between the ground terminal and the external ground to provide a low impedance path between the output terminal of the integrated circuit and an input terminal of the first switch.

2. The integrated circuit of claim 1 , wherein:

the p-channel transistor includes a p-channel insulated gate field effect transistor (IGFET) and the n-channel transistor includes an n-channel IGFET.

3. The integrated circuit of claim 1 , wherein the control circuit further comprises:

a body bias circuit to modify a body bias condition of the second switch if a break occurs in a connection between the ground terminal and the external ground.

4. The integrated circuit of claim 3 , wherein:

the second switch includes a first n-channel insulated gate field effect transistor (IGFET) and a second n-channel IGFET connected in tandem between the output terminal of the integrated circuit and the input terminal of the first switch, wherein a body of the first n-channel IGFET and a body of the second n-channel IGFET are both connected to a node between the first n-channel IGFET and the second n-channel IGFET; and

the body bias circuit includes a transistor to electrically couple the node to the input terminal of the first switch if a break occurs in a connection between the ground terminal and the external ground and to de-couple the node from the input terminal of the first switch during normal device operation.

5. The integrated circuit of claim 4 , wherein:

the body bias circuit couples the node to the ground terminal during normal device operation.

6. The integrated circuit of claim 4 , wherein the control circuit further comprises:

a third switch connected between the supply terminal and an input terminal of the first switch, the third switch to electrically couple the input terminal of the first switch to a supply potential during normal operation and to de-couple the input terminal of the first switch from the supply potential if a break occurs in a connection between the ground terminal and the external ground.

7. The integrated circuit of claim 1 , wherein:

the first switch, when turned off, prevents a flow of current to the external load through the n-channel transistor of the output amplifier.

8. A method for operating an integrated circuit having an output amplifier to drive an external load through an output terminal, the method comprising:

monitoring operation of the integrated circuit to detect whether one or more of the following events have occurred: a connection between a ground terminal of the integrated circuit and an external ground is broken and a connection between a supply terminal of the integrated circuit and an external power supply is broken; and

changing an operational condition of the output amplifier if one or more of the events have occurred, wherein changing the operational condition of the output amplifier includes switching a switch to prevent current flow through a parasitic element of the output amplifier;

wherein the external load is a pull-down load, the output amplifier includes an output stage having a p-channel transistor and an n-channel transistor, and changing an operational condition includes turning off a first switch located between the n-channel transistor and the ground terminal if a break occurs in a connection between the ground terminal and the external ground, wherein turning off the first switch includes electrically coupling an input terminal of the first switch to the output terminal of the integrated circuit and electrically de-coupling the input terminal of the first switch from the supply terminal of the integrated circuit in response to a break in the connection between the ground terminal and the external ground.

9. The method of claim 8 , wherein:

electrically coupling the input terminal of the first switch to the output terminal of the integrated circuit includes turning on a second switch, the second switch including two n-channel transistors connected in series, the two n-channel transistors having a node interconnecting them that is connected to bodies of the two n-channel transistors.

10. The method of claim 9 , wherein:

turning off the first switch further includes de-coupling the node between the two n-channel transistors of the second switch from the ground terminal.

11. The method of claim 10 , wherein:

turning off the first switch further includes coupling the node between the two n-channel transistors of the second switch to the input terminal of the first switch.

12. An integrated circuit comprising:

a supply terminal to connect to an external power supply;

a ground terminal to connect to an external ground;

an output terminal to connect to an external pull-down load;

an output amplifier coupled to the output terminal to generate an output signal on the output terminal during normal device operation, the output amplifier including an output stage having a p-channel transistor and an n-channel transistor; and

circuitry to prevent current from flowing through the output terminal if a connection between the ground terminal and the external ground is broken, the circuitry including: a first switch coupled between the n-channel transistor and the ground terminal, and a control circuit to control a conduction state of the first switch, the control circuit comprising:

a second switch connected between the output terminal of the integrated circuit and an input terminal of the first switch, wherein the second switch is configured to turn on in response to a break in a connection between the ground terminal and the external ground, the second switch including first and second transistors;

a body bias circuit configured to electrically couple the input terminal of the first switch to bodies of the first and second transistors of the second switch in response to a break in the connection between the ground terminal and the external ground; and

a third switch connected between the supply terminal and the input terminal of the first switch, wherein the third switch is configured to de-couple the input terminal of the first switch from the supply terminal in response to a break in the connection between the ground terminal and the external ground.

13. The integrated circuit of claim 12 , wherein:

the body bias circuit is configured to electrically couple the bodies of the first and second transistors of the second switch to the ground terminal and to electrically de-couple the bodies of the first and second transistors of the second switch from the input terminal of the first switch during normal integrated circuit operation.

14. The integrated circuit of claim 12 , wherein:

the first and second transistors of the second switch are connected together in series between the output terminal of the integrated circuit and an input terminal of the first switch, wherein the bodies of the first and second transistors are electrically connected to a node between the first and second transistors within the series connection.

15. The integrated circuit of claim 12 , wherein:

the circuitry to prevent current from flowing through the output terminal forms a positive feedback loop that causes the first switch to turn fully off and the output terminal to reach ground potential in response to a break in the connection between the ground terminal and the external ground.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS AT REEL 053957/FRAME 0874 Recorded Nov 1, 2023
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 065420/0572 →
PATENT SECURITY AGREEMENT Recorded Jun 22, 2023
From: ALLEGRO MICROSYSTEMS, LLC
To: MORGAN STANLEY SENIOR FUNDING, INC., AS THE COLLATERAL AGENT
Reel/Frame 064068/0459 →
RELEASE OF SECURITY INTEREST IN PATENTS (R/F 053957/0620) Recorded Jun 22, 2023
From: MIZUHO BANK, LTD., AS COLLATERAL AGENT
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 064068/0360 →
PATENT SECURITY AGREEMENT Recorded Oct 1, 2020
From: ALLEGRO MICROSYSTEMS, LLC
To: MIZUHO BANK LTD., AS COLLATERAL AGENT
Reel/Frame 053957/0620 →
PATENT SECURITY AGREEMENT Recorded Oct 1, 2020
From: ALLEGRO MICROSYSTEMS, LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 053957/0874 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2014
From: ALLEGRO MICROSYSTEMS ARGENTINA S.A.
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 034132/0858 →
CONVERSION AND NAME CHANGE Recorded Apr 10, 2013
From: ALLEGRO MICROSYSTEMS, INC.
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 030426/0178 →
CORRECTIVE ASSIGNMENT TO CORRECT THE DOCKET NUMBER TO READ ALLEG-352PUS PREVIOUSLY RECORDED ON REEL 028104 FRAME 0128. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECT DOCKET NUMBER TO READ ALLEG-352PUS. Recorded Apr 30, 2012
From: PIRCHIO, FRANCO NOEL MARTIN; VOISINE, CORY; ROMERO, HERNAN D.; MONREAL, GERARDO
To: ALLEGRO MICROSYSTEMS, INC.
Reel/Frame 028161/0569 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2012
From: PIRCHIO, FRANCO NOEL MARTIN; VOISINE, CORY; ROMERO, HERNAN D.; MONREAL, GERARDO
To: ALLEGRO MICROSYSTEMS, INC.
Reel/Frame 028104/0128 →
Continuity (1)
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