Non-volatile semiconductor memory device
A non-volatile semiconductor memory device according to an embodiment includes: a p-type semiconductor substrate; a p-type first p well which is formed in the semiconductor substrate and in which a bit line connecting transistor configured to connect a bit line of a memory cell and a sense amplifier unit is formed; and an n-type first N well which surrounds the first P well and which is configured to electrically isolate the first P well from the semiconductor substrate.
1. A non-volatile semiconductor memory device comprising:
a p-type semiconductor substrate;
a memory cell array having memory cells and a select gate transistor;
a sense amplifier unit;
a bit line connecting transistor provided between the memory cell array and the sense amplifier unit, the bit line connecting transistor connecting a bit line of the memory cells and the sense amplifier unit;
a p-type first P well formed in the semiconductor substrate, the bit line connecting transistor being formed at the first P well; and
an n-type first N well surrounding the first P well, the n-type first N well being configured to electrically isolate the first P well from the semiconductor substrate.
2. The device according to claim 1 , wherein an impurity concentration of the first P well is higher than an impurity concentration of the semiconductor substrate.
3. The device according to claim 1 , further comprising a p-type second P well in the semiconductor substrate, the second P well being formed spaced apart from the first P well and a transistor of the sense amplifier unit being formed at the second P well,
wherein an impurity concentration of the first P well is lower than an impurity concentration of the second P well, and a depth of the first P well is deeper than the second P well.
4. The device according to claim 1 , wherein a potential of the first P well is less than 0 V when data in the memory cells are read or when data are written in the memory cells.
5. The device according to claim 1 , wherein a potential of the first P well is 0 V or more when data in the memory cells are erased.
6. The device according to claim 1 , wherein the bit line connecting transistor comprises asymmetrical source/drain regions, and one of the source/drain regions comprises a LDD (Lightly Doped Drain) structure.
7. The device according to claim 6 , wherein other one of the source/drain regions of the bit line connecting transistor comprises a DDD (Double Diffused Drain) structure.
8. The device according to claim 1 , further comprising:
a p-type cell P well being formed spaced apart from the first P well in the semiconductor substrate, transistors of the memory cells being formed at the cell P well; and
an n-type second N well surrounds the cell P well, the second N well being configured to electrically isolate the cell P well from the semiconductor substrate,
wherein an impurity concentration of the first P well is lower than an impurity concentration of the cell P well, and a depth of the first P well is deeper than the cell P well.
9. The device according to claim 3 , further comprising:
a p-type cell P well formed spaced apart from the first P well in the semiconductor substrate, transistors of the memory cells being formed at the cell P well; and
an n-type second N well surrounding the cell P well, the second N well being configured to electrically isolate the cell P well from the semiconductor substrate,
wherein an impurity concentration of the first P well is lower than an impurity concentration of the cell P well, and a depth of the first P well is deeper than the cell P well.
10. The device according to claim 1 , further comprising a well potential control unit, the well potential control unit being configured to control a potential of the first P well according to an operation of reading data in the memory cells, an operation of writing data in the memory cells or an operation of erasing data from the memory cells.