Method and apparatus of transceiver calibration using substrate coupling
View Patent ↗Transceiver calibration is a critical issue for proper transceiver operation. The transceiver comprises at least one RF transmit chain and one RF receive chain. A closed loop path is formed from the digital block, the RF transmit chain, the substrate coupling, the RF receive chain back to the digital block and is used to estimate and calibrate the transceiver parameters over the operating range of frequencies. The substrate coupling eliminates the need for the additional circuitry saving area, power, and performance. In place of the additional circuitry, the digital block which performs baseband operations can be reconfigured into a software or/and hardware mode to calibrate the transceiver. The digital block comprises a processor and memory and is coupled to the front end of the RF transmit chain and the tail end of the RF receive chain.
1. A transceiver comprising:
a digital block, a transmit chain, a substrate-reactive-coupled (SRC) network, and a receive chain serially coupled to form a closed loop;
a plurality of estimation and/or compensation blocks in said digital block;
a stimulus signal from said estimation and/or compensation block applied to said transmit chain; and
said estimation and/or compensation block receives a resultant signal from said receive chain within said closed loop and estimating and/or compensating said resultant signal to calibrate said transceiver, wherein
a first estimation/compensation block disables all transmit LPFs and DACs;
a transmit LO leaks an I/Q sinusoidal signal into said transmit chain;
an up-converted I/Q sinusoidal signal coupled into said receive chain by said SRC network;
said resultant signal of said receive chain coupled into said first estimation/compensation block; and
said first estimation/compensation block compensates an I/Q imbalance of said receive chain.
2. The transceiver of claim 1 , further comprising;
a processor and a memory: and
said memory stores and retrieves all estimated or compensated outputs, wherein
said processor applies each said compensated outputs to a corresponding estimation and/or compensation block to fully calibrate said transceiver.
3. The transceiver of claim 1 , wherein
a second estimation/compensation block disables all transmit LPFs and DACs;
said second estimation/compensation block adjusts an input DC value and/or internal bias point of all transmit mixers;
a transmit LO leaks an I/Q sinusoidal signal into said transmit chain;
an up-converted I/Q sinusoidal signal is coupled into said receive chain by said SRC network; and
said resultant signal of said receive chain coupled into said second estimation/compensation block, whereby
said second estimation/compensation block compensates said transmit LO leakage.
4. The transceiver of claim 1 , further comprising:
a third estimation/compensation block enables all transmit LPF's and DAC's;
said third estimation/compensation block generates and couples I/Q signals into said transmit chain;
up-converted I/Q signals are coupled into said receive chain by said SRC network; and
said resultant output of said receive chain coupled into said third estimation/compensation block, whereby
said third estimation/compensation block compensates an I/Q imbalance of said transmit chain.
5. The transceiver of claim 1 , further comprising:
a fourth compensation block generates and couples I/Q signals into said transmit chain;
said fourth compensation block adjusts all transmit and receive LPFs to a maximum bandwidth;
said fourth compensation block adjusts said transmit or receive LPFs to a cutoff frequency and stores first results from said LPFs into a memory:,
said fourth compensation block adjusts all LPFs to said maximum bandwidth; and
said fourth compensation block adjusts said other LPFs to said cutoff frequency and stores second results from said LPL's into said memory.
6. A transceiver comprising:
a digital block, a transmit chain, a substrate-reactive-coupled (SRC) network, and a receive chain serially coupled to form a closed loop;
a plurality of estimation and/or compensation blocks in said digital block;
a stimulus signal from said estimation and/or compensation block applied to said transmit chain; and
said estimation and/or compensation block receives a resultant signal from said receive chain within said closed loop and estimating and/or compensating said resultant signal to calibrate said transceiver, wherein
a second estimation/compensation block disables all transmit LPFs and DACs;
said second estimation/compensation block adjusts an input DC value and/or internal bias point of all transmit mixers;
a transmit LO leaks an I/Q sinusoidal signal into said transmit chain;
an up-converted I/Q sinusoidal signal is coupled into said receive chain by said SRC network; and
said resultant signal of said receive chain coupled into said second estimation/compensation block, whereby
said second estimation/compensation block compensates said transmit LO leakage.
7. The transceiver of claim 6 , further comprising;
a processor and a memory; and
said memory stores and retrieves all estimated or compensated outputs, wherein
said processor applies each said compensated outputs to a corresponding estimation and/or compensation block to fully calibrate said transceiver.
8. The transceiver of claim 6 , wherein
a first estimation/compensation block, disables all transmit LPFs and DACs;
a transmit LO leaks an I/Q sinusoidal signal into said transmit chain;
an up-converted I/Q sinusoidal signal coupled into said receive chain by said SRC network;
said resultant signal of said receive chain coupled into said first estimation/compensation block; and
said first estimation/compensation block compensates an I/Q imbalance of said receive chain.
9. The transceiver of claim 6 , further comprising:
a third estimation/compensation block enables all transmit LPFs and DACs;
said third estimation/compensation block generates and couples I/Q signals into said transmit chain;
up-converted I/Q signals are coupled into said receive chain by said SRC network; and
said resultant output of said receive chain coupled into said third estimation/compensation block, whereby
said third estimation/compensation block compensates an I/Q imbalance of said transmit chain.
10. The transceiver of claim 6 , further comprising:
a fourth compensation block generates and couples I/Q signals into said transmit chain;
said fourth compensation block adjusts all transmit and receive LPFs to a maximum bandwidth:
said fourth compensation block adjusts said transmit or receive LPFs to a cutoff frequency and stores first results from said LPFs into a memory;
said fourth compensation block adjusts all LPFs to said maximum bandwidth; and
said fourth compensation block adjusts said other LPFs to said cutoff frequency and stores second results from said LPFs into said memory.
11. A transceiver comprising:
a digital block, a transmit chain, a substrate-reactive-coupled (SRC) network, and a receive chain serially coupled to form a closed loop;
a plurality of estimation and/or compensation blocks in said digital block;
a stimulus signal from said estimation and/or compensation block applied to said transmit chain:
said estimation and/or compensation block receives a resultant signal from said receive chain within said closed loop and estimating, and/or compensating said resultant signal to calibrate said transceiver;
a fourth compensation block generates and couples I/Q signals into said transmit chain;
said fourth compensation block adjusts all transmit and receive LPFs to a maximum bandwidth;
said fourth compensation block adjusts said transmit or receive LPFs to a cutoff frequency and stores first results from said LPFs into a memory;
said fourth compensation block adjusts all LPFs to said maximum bandwidth; and
said fourth compensation block adjusts said other LPFs to said cutoff frequency and stores second results from said LPFs into said memory.
12. The transceiver of claim 11 , further comprising:
a processor and a memory; and
said memory stores and retrieves all estimated or compensated outputs, wherein
said processor applies each said compensated outputs to a corresponding estimation and/or compensation block to fully calibrate said transceiver.
13. The transceiver of claim 11 , wherein
a first estimation/compensation block disables all transmit LPFs and DACs:
a transmit LO leaks an I/Q sinusoidal signal into said transmit chain;
an up-converted I/Q sinusoidal signal coupled into said receive chain by said SRC network;
said resultant signal of said receive chain coupled into said first estimation/compensation block; and
said first estimation/compensation block compensates an I/Q imbalance of said receive chain.
14. The transceiver of claim 11 , wherein
a second estimation/compensation block disables all transmit LPFs and DACs;
said second estimation/compensation block adjusts an input DC value and/or internal bias point of all transmit mixers;
a transmit LO leaks an I/Q sinusoidal signal into said transmit chain;
an up-converted I/Q sinusoidal signal is coupled into said receive chain by said SRC network; and
said resultant signal of said receive chain coupled into said second estimation/compensation block, whereby
said second estimation/compensation block compensates said transmit LO leakage.
15. The transceiver of claim 11 , further comprising:
a third estimation/compensation block enables all transmit LPFs and DACs;
said third estimation/compensation block generates and couples I/Q signals into said transmit chain;
up-converted I/Q signals are coupled into said receive chain by said SRC network; and
said resultant output of said receive chain coupled into said third estimation/compensation block, whereby
said third estimation/compensation block compensates an imbalance of said transmit chain.