IP Library Patent Application 13443718
Patent Application
App. No. 13/443,718

CAPACITANCE SENSOR WITH SENSOR CAPACITANCE COMPENSATION

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Quick Facts
Patent No.
US None
App. No.
13/443,718
Abstract

A capacitance sensing circuit may include a switching circuit configured to generate a sensor current by charging and discharging a capacitive sensor electrode, and a current mirror that generates a mirror current based on the sensor current. Based on the mirror current, a measurement circuit generates an output signal representative of a capacitance of the capacitive sensor electrode.

Claims (36)

1 - 20 . (canceled)

21 . A capacitance sensing circuit, comprising:

a switching circuit configured to generate a sensor current by charging and discharging a capacitive sensor electrode;

a current mirror coupled with the switching circuit, wherein the current mirror is configured to generate a mirror current based on the sensor current; and

a measurement circuit coupled with the current mirror, wherein the measurement circuit is configured to generate, based on the mirror current, an output signal representative of a capacitance of the capacitive sensor electrode.

22 . The capacitance sensing circuit of claim 21 , wherein the current mirror is further configured to generate the mirror current by amplifying the sensor current.

23 . The capacitance sensing circuit of claim 21 , wherein the current mirror further comprises a first transistor and a second transistor, wherein the sensor current flows through the first transistor, and wherein the mirror current flows through the second transistor.

24 . The capacitance sensing circuit of claim 23 , wherein a gate of each of the first transistor and the second transistor is coupled with the switching circuit.

25 . The capacitance sensing circuit of claim 23 , wherein the first transistor is configured to supply the sensor current to the switching circuit, and wherein the second transistor is configured to supply the mirror current to the measurement circuit.

26 . The capacitance sensing circuit of claim 21 , wherein the first transistor is coupled with the switching circuit, and wherein the second transistor is coupled with the measurement circuit.

27 . The capacitance sensing circuit of claim 21 , further comprising a current source coupled with the capacitive sensor electrode, wherein the current source is configured to supply a compensation current to the capacitive sensor.

28 . The capacitance sensing circuit of claim 21 , wherein the measurement circuit comprises an integration capacitor and a timer configured to detect a rise time for a voltage of the integration capacitor to reach a reference voltage.

29 . The capacitance sensing circuit of claim 28 , wherein the integration capacitor is contained within an integrated circuit chip.

30 . A method, comprising:

generating a sensor current by charging and discharging a capacitive sensor electrode;

generating a mirror current based on the sensor current using a current mirror; and

generating, based on the mirror current, an output signal representative of a capacitance of the capacitive sensor electrode.

31 . The method of claim 30 , wherein generating the mirror current further comprises amplifying the sensor current.

32 . The method of claim 30 , wherein generating the mirror current further comprises:

conducting the sensor current through a first transistor of the current mirror; and

conducting the mirror current through a second transistor of the current mirror.

33 . The method of claim 30 , further comprising supplying a compensation current to the capacitive sensor.

34 . The method of claim 33 , wherein the compensation current is approximately equal to an amount of current attributable to a baseline capacitance of the capacitive sensor.

35 . The method of claim 30 , wherein generating the output signal further comprises:

charging an integration capacitor using the mirror current; and

detecting a rise time for a voltage of an integration capacitor to reach a reference voltage.

36 . The method of claim 35 , wherein the integration capacitor is contained within an integrated circuit chip.

37 . A system, comprising:

a capacitive sensor electrode; and

an integrated circuit chip having an input coupled with the capacitive sensor electrode, wherein the integrated circuit chip comprises:

a switching circuit configured to generate a sensor current by charging and discharging the capacitive sensor electrode,

a current mirror coupled with the switching circuit, wherein the current mirror is configured to generate a mirror current based on the sensor current, and

a measurement circuit coupled with the current mirror, wherein the measurement circuit is configured to generate, based on the mirror current, an output signal representative of a capacitance of the capacitive sensor electrode.

38 . The system of claim 37 , wherein the current mirror is further configured to generate the mirror current by amplifying the sensor current.

39 . The system of claim 37 , wherein the current mirror further comprises a first transistor and a second transistor, wherein the sensor current flows through the first transistor, and wherein the mirror current flows through the second transistor.

40 . The system of claim 37 , wherein the switching circuit is configured to charge the integration capacitor at a rate positively correlated with the capacitance of the capacitive sensor electrode.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040028/0054 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 13, 2015
From: MAHARYTA, ANDRIY; RYSHTUN, ANDRIY
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036785/0190 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →