A memory circuit may include a shift register ring including single-bit shift registers. The circuit may include a clock connected to the shift registers to shift bits within the shift register ring, and a counter connected to the clock and indicating positions of the bits in the shift register ring.
1. A memory circuit comprising:
a shift register ring including single-bit shift registers;
a clock connected to the shift registers to shift bits within the shift register ring;
a counter connected to the clock and indicating positions of the bits in the shift register ring; and
a clock disable circuit connected to an output of the clock to inhibit a clock propagation to the counter and the shift registers when writing to the shift registers.
2. The circuit of claim 1 , comprising:
a shift register selection circuit connected to the counter and the shift registers to select a shift register based on a position indicated by the counter.
3. The circuit of claim 2 , wherein the shift register selection circuit comprises a multiplexer including a selector connected to the counter and outputs connected to the shift registers, wherein a counter value from the counter selects an output of the multiplexer corresponding to a current position of the bits.
4. The circuit of claim 2 , wherein the bits include bits D 0 -Dn, the shift registers includes shift registers SR 0 -SRn, the shift register selection circuit includes a multiplexer for each bit D 0 -Dn, and each multiplexer includes a selector connected to the counter to select a corresponding output of each multiplexer to read or write the bits D 0 -Dn from the shift registers SR 0 -SRn according to a current position of the bits D 0 -Dn indicated by a current value of the counter.
5. The circuit of claim 4 , wherein each multiplexer includes outputs Q 0 -Qn connected to a corresponding set of the shift registers to read or write the bits D 0 -Dn from the shift registers SR 0 -SRn according to the current position of the bits D 0 -Dn indicated by the current value of the counter.
6. The circuit of claim 5 , wherein the outputs Q 0 -Qn for the multiplexer for D 0 are connected to the shift registers SR 0 -SRn respectively, the outputs Q 0 -Qn−1 for the multiplexer for D 1 are connected to the shift registers SR 1 -SRn−1 respectively, and so on for each of the multiplexers for each bit D 0 -Dn wherein the output Q 0 for the multiplexer for Dn is connected to the shift register SRn.
7. The circuit of claim 2 , wherein each shift register comprises a D flip-flop storing only a single bit of data, and the shift register selection circuit is connected to the input and the output of each D flip-flop to read or write data from the flip-flops.
8. The circuit of claim 1 , wherein each shift register includes a zeroize input and each shift register is to simultaneously receive a zeroize active signal to reset each bit stored in the shift registers simultaneously.
9. The circuit of claim 1 , wherein for each clock pulse generated by the clock, each bit is shifted to a next shift register in the ring, and the counter is incremented by one unless the bits are in a final position, and then the counter is reset to 0.
10. A circuit comprising:
a clock connected to single-bit shift registers in a shift register ring to shift bits within the shift register ring;
a counter connected to the clock and indicating a current position of the bits in the shift register ring; and
a shift register selection circuit connected to the counter and the shift registers to select shift registers based on a position indicated by the counter,
wherein for each clock pulse generated by the clock, each bit is shifted to a next shift register in the ring, and the counter is incremented by one unless the bits are in a final position, and then the counter is reset to 0.
11. The circuit of claim 10 , wherein the bits include bits D 0 -Dn, the shift registers includes shift registers SR 0 -SRn, the shift register selection circuit includes a multiplexer for each bit D 0 -Dn, and each multiplexer includes a selector connected to the counter to select a corresponding output of each multiplexer to read or write the bits D 0 -Dn from the shift registers SR 0 -SRn according to a current position of the bits D 0 -Dn indicated by a current value of the counter.
12. The circuit of claim 10 , wherein the shift register selection circuit comprises N number of multiplexers, wherein N is a number of bits in a word, and the counter has N number of counter bits, and a number of low order bits of the counter comprised of log 2N select a word in the shift registers, and the remaining bits in the counter represent an offset into the selected word.
13. A method of shifting bits in a shift register ring including single-bit shift registers comprising:
shifting the bits in the shift register ring for each clock pulse generated by a clock;
incrementing a counter by one for each clock pulse unless the bits are in a home position, and then resetting the counter to 0, wherein the counter indicates a current position of the bits in the shift register ring; and
selecting a shift register based on a current position indicated by the counter to read or write data to the shift registers.
14. The method of claim 13 , comprising:
using a clock disable circuit connected to an output of the clock to inhibit a clock propagation to the counter and the shift registers when writing to the shift registers.