Semiconductor device including memory cell having capacitor
A semiconductor device includes a semiconductor substrate; a memory cell array including a plurality of memory cells formed on the semiconductor substrate and arranged in a matrix in a first direction and a second direction on the surface of the semiconductor substrate; a plurality of sense amplifiers formed on the semiconductor substrate and including a first sense amplifier and a second sense amplifier; and a plurality of bit lines extending along the first direction above the memory cell array, and arranged side by side in the second direction, wherein the plurality of bit lines include a first bit line pair formed in a first wiring layer and a second bit line pair formed in a second wiring layer located above the first wiring layer.
1. A semiconductor device manufacturing method comprising:
forming, in a semiconductor substrate, grooves for defining active regions, each active region including a transistor region formed with a selection transistor of a memory cell, and a capacitor region formed with a capacitor of the memory cell;
filling the grooves in with an element isolation insulating film;
removing at least a part of the element isolation insulating film formed on both sides of the capacitor region to expose sidewalls of the active regions;
sequentially forming a dielectric film and a first conductive film on the active regions and the sidewalls;
patterning the first conductive film so that a gate electrode made of the first conductive film is formed in the transistor region, and that a counter electrode made of the first conductive film is formed in the capacitor region;
forming a lower interlayer insulating film for covering the gate electrode and the counter electrode;
forming a first metal wiring layer on the lower interlayer insulating film;
patterning the first metal wiring layer to form a first bit line;
forming a first interlayer insulating film for covering the first bit line;
forming a second metal wiring layer on the first interlayer insulating film; and
patterning the second metal wiring layer to form a second bit line.
2. The semiconductor device manufacturing method according to claim 1 , further comprising:
forming a second interlayer insulating film for covering the second bit line;
forming a third metal wiring layer on the second interlayer insulating film; and
patterning the third metal wiring layer to form a word line.