Method and apparatus for improving the performance of a DAC switch array
One of the critical design parameters occurs when a digital signal is converted into an analog signal. As the supply voltage drops to less than 2 times of threshold voltage to reduce leakage and save power, generating a relative large swing with a resistor-ladder DAC becomes more difficult. For a 5 bit DAC, 32 sub-arrays are used to select the appropriate voltage from the series coupled resistor network. Each sub-array uses p-channel transistors where the sub-array extracting the lowest voltage 700 mV only has a 100 mV of gate to source voltage. To compensate for the reduced gate to source voltage, the sub-arrays are partitioned into four groups. In each group, the p-channel width is increased from 2 um to 5 um, as the tap voltage drops from 1.2 V to 0.7 V. This allows the p-channel transistor with a small gate to source voltage to have a larger width thereby improving performance.
1. An apparatus comprising:
a plurality of resistors coupled in a series resistor network;
a first end of said series coupled resistor network;
a second end of said series coupled resistor network;
a plurality transistors coupled to each tap point of said series coupled resistor network; wherein
said plurality of transistors coupled to each said tap point from said first end to said second end increase in channel width;
a first power supply coupled to said first end;
an adjustable current source coupled to said second end; and
a second power supply coupled to said adjustable current source.
2. The apparatus of claim 1 , wherein
said first power supply is VDD;
said second power supply is VSS; and
said plurality of transistors are p-channel transistors.
3. The apparatus of claim 1 , wherein
said first power supply is VSS;
said second power supply is VDD; and
said plurality of transistors are n-channel transistors.
4. The apparatus of claim 1 , further comprising:
a first decoder to enable a first plurality of said plurality of transistors for Q signal voltages; and
a second decoder to enable a remainder of said plurality of transistors for I signal voltages.
5. The apparatus of claim 4 , wherein
said Q signal voltages includes a Q compliment voltage, and
said I signal voltages includes an I compliment voltage.
6. The apparatus of claim 5 , further comprising:
a first differential isolation buffer couples said Q signal voltages to a Q filter; and
a second differential isolation buffer couples said I signal voltages to an I filter; wherein
said isolation buffers provide a constant output impedance to said filters regardless of an output impedance exhibited at said tap point of said series coupled resistor network.
7. An apparatus comprising:
a plurality of resistors coupled in a series resistor network;
a first end of said series coupled resistor network;
a second end of said series coupled resistor network;
a plurality of transistors coupled to each tap point of said series coupled resistor network; and
said plurality of transistors coupled to each said tap point from said first end to said second end are combined into several consecutive groups; wherein a transistor channel width in each said group increases from said first end to said second end.
8. The apparatus of claim 7 , further comprising:
a first power supply coupled to said first end;
an adjustable current source coupled to said second end; and
a second power supply coupled to said adjustable current source.
9. The apparatus of claim 8 , wherein
said first power supply is VDD;
said second power supply is VSS; and
said plurality of transistors are p-channel transistors.
10. The apparatus of claim 8 , wherein
said first power supply is VSS;
said second power supply is VDD; and
said plurality of transistors are n-channel transistors.
11. The apparatus of claim 8 , further comprising;
a first decoder to enable a first plurality of said plurality of transistors for Q signal voltages; and
a second decoder to enable a remainder of said plurality of transistors for I signal voltages.
12. The apparatus of claim 11 , wherein
said Q signal voltages includes a Q compliment voltage, and
said I signal voltages includes an I compliment voltage.
13. The apparatus of claim 12 , further comprising:
a first differential isolation buffer couples said Q signal voltages to a Q filter; and
a second differential isolation buffer couples said I signal voltages to an I filter; wherein
said isolation buffers provide a constant output impedance to said filters regardless of an output impedance exhibited at said tap point of said series coupled resistor network.
14. A method of minimizing DAC (Digital to Analog Converter) delay comprising the steps of:
coupling a plurality of resistors in a series resistor network;
coupling a first power supply to a first end of said series coupled resistor network;
coupling a second power supply to a second end of said series coupled resistor network;
coupling a plurality of transistors to each tap point of said series coupled resistor network; and
partitioning said plurality of transistors coupled to said tap points from said first end to said second end into several consecutive groups;
wherein a transistor channel width of each said group increases from said first end to said second end.
15. The method of claim 14 , further comprising the steps of:
coupling a first power supply to said first end;
coupling an adjustable current source to said second end; and
coupling a second power supply to said adjustable current source.
16. The method of claim 14 , wherein
said first power supply is VDD;
said second power supply is VSS; and
said plurality of transistors are p-channel transistors.
17. The method of claim 14 , wherein
said first power supply is VSS;
said second power supply is VDD; and
said plurality of transistors are n-channel transistors.
18. The method of claim 14 , further comprising the steps of:
enabling a first plurality of said plurality of transistors with a first decoder to generate Q signal voltages; and
enabling a remainder of said plurality of transistors with a second decoder to generate I signal voltages.
19. The method of claim 14 , further comprising the steps of:
including the compliment voltage of said Q signal voltages, and
including the compliment voltage of said I signal voltages.