SEMICONDUCTOR DEVICE HAVING DUMMY PATTERN AND DESIGN METHOD THEREOF
Disclosed herein is the semiconductor substrate, wiring patterns and dummy patterns. A margin region is formed around the wiring pattern. The dummy region is further formed around the margin region. The dummy patterns are formed in the dummy region. The dummy patterns are arranged along the extending direction of the dummy region. Margin regions and dummy regions are allocated alternately with respect to the wiring pattern.
1 . A semiconductor device comprising:
a wiring pattern formed on a wiring region;
a dummy pattern formed on a dummy region; and
a margin region being free from the wiring pattern and the dummy pattern, the margin region having a substantially constant width between the wiring region and the dummy region.
2 . The semiconductor device as claimed in claim 1 , wherein a plurality of the dummy patterns are arranged on an extending direction of the dummy region.
3 . The semiconductor device as claimed in claim 2 , wherein at least two of the dummy patterns have different shapes from each other.
4 . The semiconductor device as claimed in claim 2 , wherein
the dummy region has a first region extending in a first direction, a second region extending in a second direction different from the first direction, and a corner portion overlapping the first and second region, and
one of the dummy patterns is arranged on the corner portion of the dummy region.
5 . The semiconductor device as claimed in claim 2 , wherein the dummy patterns have a rectangular shape in which a longitudinal direction thereof is arranged in the extending direction.
6 . The semiconductor device as claimed in claim 2 , wherein
the wiring pattern includes first and second wiring patterns extending in parallel,
the margin region includes first and second margin regions each surrounding corresponding one of the first and second wiring patterns, and
at least one of the dummy patterns is provided between the first and second margin regions.
7 . The semiconductor device as claimed in claim 6 , wherein the at least one of the dummy patterns that is provided between the first and second margin regions has a width wider than twice as wide as other of the dummy patterns and narrower than sum of twice as wide as other of the dummy patterns and the constant width of the margin region.
8 . The semiconductor device as claimed in claim 1 , wherein a plurality of the margin regions and a plurality of the dummy regions are alternately formed around the wiring pattern.
9 . A semiconductor device comprising:
a wiring pattern to transfer a signal or to be supplied with a specific voltage and including a first edge and a second edge intersect with the first edge;
a plurality of first patterns provided along to the first edge and aligned in a first straight line;
a plurality of second patterns provided along to the second edge and aligned in a second straight line; and
a third pattern of a regular tetragon formed on an intersection of the first and second straight lines.
10 . The semiconductor device according to claim 9 , wherein the shape of at least one of the first patterns is different from the third pattern.
11 . The semiconductor device according to claim 9 , further comprising a plurality of fourth patterns provided to a third edge in parallel with the first edge and aligned in a third straight line, a width of at least one of the plurality of fourth patterns being lager than that of the plurality of first patterns.
12 . The semiconductor device according to claim 9 , wherein the plurality of first patterns and the plurality of second patterns formed by a metal.
13 . The semiconductor device according to claim 9 , wherein each of the plurality of first patterns and the plurality of second patterns is in an electrically floating state.