Semiconductor device having a multilayer interconnection structure
View Patent ↗A semiconductor device includes first and second conductor patterns embedded in a first interlayer insulation film and a third conductor pattern embedded in a second interlayer insulation film, the third conductor pattern including a main part and an extension part, the extension part being electrically connected to the first conductor pattern by a first via-plug, the extension part having a branched pattern closer to the main part compared with the first conductor pattern, the branched pattern making a contact with the second conductor pattern via a second via-plug, each of the main part, extension part including the branched pattern, first via-plug and second via-plug forming a damascene structure.
1. A semiconductor device comprising:
a substrate;
a first interlayer insulation film formed above said substrate;
a first conductor pattern formed in said first interlayer insulation film and a second conductor pattern formed in said first interlayer insulation film, said second conductor pattern being separated from said first conductor pattern in a plan view;
a second interlayer insulation film formed above said first insulation film;
a third conductor pattern formed in said second interlayer insulation film;
an extension part formed in said second interlayer insulation film and connected to said third conductor pattern in a plan view, a width of said extension part being narrower than a width of said third conductor pattern;
a first via-plug formed on said first conductor pattern and under said extension part;
a branched pattern formed in said second interlayer insulation film and connected to said extension part in a plan view; and
a second via-plug formed on said second conductor pattern and under said branched pattern.
2. The semiconductor device as claimed in claim 1 , wherein said third conductor pattern, said extension pattern, said branched pattern, said first via-plug and said second via-plug form a dual damascene structure together with said second interlayer insulation film.
3. The semiconductor device as claimed in claim 1 , wherein said extension part and said branched pattern are located out of the said third conductor pattern in a plan view.
4. The semiconductor device as claimed in claim 1 , wherein a distance from said third conductor pattern to said second via-plug via said extension part and said branched pattern is shorter than a distance from said third conductor pattern to said first via-plug via a part of said extension part and said branched pattern in a plan view.