Semiconductor memory, system, and method of operating semiconductor memory

1. A semiconductor memory comprising:

memory cells disposed in a matrix;

a first selection unit which selects any of first signal lines respectively connected to memory cell lines arranged in a first direction, in response to an access request to access the memory cells;

a second selection unit which selects any of second signal lines respectively connected to the memory cell lines arranged in a second direction intersecting with the first direction, after the first selection unit starts operating;

a first voltage generation unit which generates a first power supply voltage to be supplied to the first selection unit;

a second voltage generation unit which generates a second power supply voltage to be supplied to the second selection unit, when a start-up signal is in an activating state;

a switch which short-circuits a first power supply line supplied with the first power supply voltage and a second power supply line supplied with the second power supply voltage to each other, when a short-circuit signal is in the activating state; and

a power supply voltage control unit which activates the start-up signal in response to the access request, activates the short-circuit signal after a predetermined time elapses since activation of the start-up signal, deactivates the short-circuit signal after completion of access operations based on the access request, and deactivates the start-up signal in response to deactivation of the short-circuit signal.

2. The semiconductor memory according to claim 1 , wherein the power supply voltage control unit activates the short-circuit signal in a period after the second power supply voltage reaches a first voltage until the second selection unit starts operating.

3. The semiconductor memory according to claim 2 , further comprising:

a command control unit which receives a read/write request which denotes read operations or write operations after receiving the access request, wherein

the first selection unit starts operating in response to the access request,

the second selection unit starts operating in response to the read/write request, and

the power supply voltage control unit activates the short-circuit signal in a period after the second power supply voltage reaches the first voltage until the read/write request reception.

4. The semiconductor memory according to claim 1 , wherein the power supply voltage control unit comprises:

a counter which counts the number of clock cycles following the access request; and

a detection circuit which activates the short-circuit signal when the counter counts a predetermined times.

5. The semiconductor memory according to claim 4 , comprising a register which sets the number of clock cycles in a period from a time when an internal circuit starts operating to a time when the internal circuit outputs a signal,

wherein the power supply voltage control unit includes a conversion circuit which generates the predetermined value in accordance with a value set by the register.

6. The semiconductor memory according to claim 1 , wherein the power supply voltage control unit comprises a delay circuit which activates the short-circuit signal after the predetermined time elapses since activation of the start-up signal.

7. The semiconductor memory according to claim 1 , wherein the power supply voltage control unit deactivates the short-circuit signal when the power supply voltage control unit does not receive the access request for a predetermined period after completion of the access operations.

8. The semiconductor memory according to claim 1 , wherein the second selection unit comprises an address decoder which decodes an address signal which is supplied to select the second signal line.

9. The semiconductor memory according to claim 1 , wherein the second selection unit comprises a latch circuit which holds a data signal which is transmitted to the second signal line and input to and output from the memory cells.

10. A system comprising:

the semiconductor memory according to claim 1 ; and

a controller which controls access to the semiconductor memory.

11. A method of operating a semiconductor memory having memory cells disposed in a matrix, a first selection unit which selects any of first signal lines respectively connected to memory cell lines arranged in a first direction in response to an access request to gain access to the memory cells, a second selection unit which selects any of second signal lines respectively connected to the memory cell lines arranged in a second direction intersecting with the first direction after the first selection unit starts operating, and a switch which short-circuits a first power supply line supplying a first power supply voltage to the first selection unit and a second power supply line supplying a second power supply voltage to the second selection unit to each other when a short-circuit signal is in an activating state,

the method comprising:

generating the first power supply voltage to be supplied to the first selection unit;

activating a start-up signal when the access request to the memory cells is received;

generating the second power supply voltage to be supplied to the second selection unit when the start-up signal is in the activating state;

activating the short-circuit signal after a predetermined time elapses since activation of the start-up signal; and

deactivating the short-circuit signal after completion of access operations in response to the access request and deactivating the start-up signal in response to deactivation of the short-circuit signal.

12. The semiconductor memory operating method according to claim 11 , wherein the short-circuit signal is activated in a period from a time when the second power supply voltage reaches a first voltage to a time when the second selection unit starts operating.

13. The semiconductor memory operating method according to claim 12 , comprising:

receiving a read/write request which denotes read operations or write operations after receiving the access request, wherein

the first selection unit starts operating in response to the access request, and

the second selection unit starts operating in response to the read/write request,

the short-circuit signal being activated in a period from a time when the second power supply voltage reaches the first voltage to a time when the read/write request is received.

14. The semiconductor memory operating method according to claim 11 , comprising activating the short-circuit signal when a counter which counts the number of clock cycles following the access request counts a predetermined times.

15. The semiconductor memory operating method according to claim 14 , comprising generating the predetermined value in accordance with a value set by a register which sets the number of clock cycles to be given in a period from a time when an internal circuit starts operating to a time when the internal circuit outputs a signal.

16. The semiconductor memory operating method according to claim 11 , comprising deactivating the short-circuit signal when the access request is not received for a predetermined period after completion of the access operations.