Method and system for embedded high performance reconfigurable firmware cipher
View Patent ↗A firmware cipher component is provided which can be configured and programmed to efficiently implement a broad range of cryptographic ciphers while accelerating their processing. This firmware cipher component allows an ASIC to support multiple cipher algorithms while accelerating the operations beyond speeds conventionally achieved by software or firmware only solutions. This system combines cryptographic specific custom instructions with hardware based data manipulation accelerators. The cryptographic specific custom instructions and hardware accelerators may support both block and stream ciphers. Thus, the system may be reconfigured, allowing the cipher algorithm to change without halting the system. Further, embedding the Firmware Programmable Cipher within an ASIC may allow future capabilities to be supported in secure applications.
1. A configurable data processing system for executing a cryptographic protocol, comprising:
an input configured to receive data to be processed according to a cryptographic calculation;
a configurable processor configured to execute the cryptographic calculation on the input data based on the cryptographic protocol, comprising custom firmware instructions configured to cause the processor to execute the cryptographic calculation; and
two or more configurable hardware cipher data accelerators connected to the configurable processor and configured to process portions of input data to be processed, wherein the two or more configurable hardware cipher accelerators further comprise two of: (1) a butterfly/inverse butterfly network, (2) a substitution box, (3) a programmable logic array, and (4) a linear feedback shift register.
2. The data processing system of claim 1 , wherein the two or more configurable hardware cipher accelerators further comprise (1) a butterfly/inverse butterfly network, (2) a substitution box, (3) a programmable logic array, and (4) a linear feedback shift register.
3. The data processing system of claim 1 , further comprising an output configured to buffer and output data resulting from executing the cryptographic calculation on the input data.
4. The data processing system of claim 1 , further comprising a security association buffer configured to store a cryptographic key to be used during the cryptographic calculation.
5. The data processing system of claim 1 , wherein in one or more of the one or more configurable hardware cipher data accelerators is a butterfly/inverse butterfly network which is connected to a look up table.
6. A method data processing system for executing a cryptographic protocol, comprising:
configuring two or more configurable hardware cipher data accelerators connected to a configurable processor to process portions of data to be processed according to a cryptographic calculation based on the cryptographic protocol;
inputting the data to be processed according to the cryptographic calculation to an ingress buffer;
executing, by the configurable processor, the cryptographic calculation on the input data based on custom firmware instructions that cause the configurable processor to execute the cryptographic calculation; and
activating one or more of the configurable hardware cipher data accelerators to process portions of the input data, wherein the two or more configurable hardware cipher accelerators further comprise two of: (1) a butterfly/inverse butterfly network, (2) a substitution box, (3) a programmable logic array, and (4) a linear feedback shift register.
7. The method of claim 6 , wherein the two or more configurable hardware cipher accelerators further comprise (1) a butterfly/inverse butterfly network, (2) a substitution box, (3) a programmable logic array, and (4) a linear feedback shift register.
8. The method of claim 6 , further comprising outputting data resulting from executing the cryptographic calculation on the input data.
9. The method of claim 6 , further comprising storing a cryptographic key to be used during the cryptographic calculation in a security association buffer.
10. The method of claim 6 , wherein one or more of the configurable hardware cipher data accelerators is a butterfly/inverse butterfly network which is connected to a look up table.