Method to shorten crystal oscillator's startup time

1. An oscillator circuit comprising:

an amplifier including at least two terminals for receiving a crystal; and

an automatic amplitude control loop coupled to the amplifier comprising biasing circuitry switched between a first operational mode and a second operational mode;

wherein, in both the first operational mode and the second operational mode, the automatic amplitude control loop has a non-zero gain that causes the oscillator circuit to oscillate;

wherein the biasing circuitry comprises first and second PMOS transistor circuits, each transistor circuit comprising an unswitched PMOS transistor and a switched PMOS transistor.

2. The oscillator circuit of claim 1 wherein the first operational mode occurs during an initial time period and the second operational mode occurs after the initial time period is expired.

3. An oscillator circuit comprising:

an amplifier including at least two terminals for receiving a crystal; and

an automatic amplitude control loop coupled to the amplifier comprising biasing circuitry switched between a first operational mode and a second operational mode;

wherein, in both the first operational mode and the second operational mode, the automatic amplitude control loop has a non-zero gain that causes the oscillator circuit to oscillate;

wherein the biasing circuitry comprises first and second NMOS transistor circuits, each transistor circuit comprising an unswitched NMOS transistor and a switched NMOS transistor.

4. The oscillator circuit of claim 3 wherein the first operational mode occurs during an initial time period and the second operational mode occurs after the initial time period is expired.

5. An oscillator comprising:

first, second, and third PMOS transistors having a common gate connection;

a first switching transistor coupled to the first PMOS transistor;

a second switching transistor coupled to the second PMOS transistor; and

first, second, and third NMOS transistors coupled to the first, second, and third PMOS transistors;

wherein the third NMOS transistor has two terminals for receiving an external crystal;

wherein the first and second PMOS transistors, the first and second switching transistors, and the first and second NMOS transistors comprise an automatic amplitude control loop;

wherein the first and second switching transistors are switched between a first operational mode and a second operational mode;

wherein, in both the first operational mode and the second operational mode, the automatic amplitude control loop has a non-zero gain that causes the oscillator circuit to oscillate.

6. The oscillator of claim 5 wherein the first switching transistor comprises a PMOS transistor having a gate coupled to a switch.

7. The oscillator of claim 5 wherein the second switching transistor comprises a PMOS transistor having a gate coupled to a switch.

8. The oscillator of claim 5 wherein the first, second, and third PMOS transistors each comprise a source coupled to a supply voltage.

9. The oscillator of claim 5 wherein the first, second, and third NMOS transistors each comprise a source coupled to ground.

10. The oscillator of claim 5 wherein the first and second NMOS transistors are coupled together through a low pass filter.

11. The oscillator of claim 5 wherein the second and third NMOS transistors are coupled together through a capacitor.

12. The oscillator of claim 5 further comprising a control circuit for providing a switching control circuit to the first and second switching transistors.

13. An oscillator comprising:

first, second, and third PMOS transistors;

first, second, and third NMOS transistors having a common gate connection coupled to the first, second, and third PMOS transistors;

a first switching transistor coupled to the first NMOS transistor; and

a second switching transistor coupled to the second NMOS transistor;

wherein the third PMOS transistor has two terminals for receiving an external crystal;

wherein the first and second PMOS transistors, the first and second switching transistors, and the first and second NMOS transistors comprise an automatic amplitude control loop;

wherein the first and second switching transistors are switched between a first operational mode and a second operational mode;

wherein, in both the first operational mode and the second operational mode, the automatic amplitude control loop has a non-zero gain that causes the oscillator circuit to oscillate.

14. The oscillator of claim 13 wherein the first switching transistor comprises an NMOS transistor having a gate coupled to a switch.

15. The oscillator of claim 13 wherein the second switching transistor comprises an NMOS transistor having a gate coupled to a switch.

16. The oscillator of claim 13 wherein the first, second, and third PMOS transistors each comprises a source coupled to a supply voltage.

17. The oscillator of claim 13 wherein the first, second, and third NMOS transistors each comprises a source coupled to ground.

18. The oscillator of claim 13 wherein the first and second PMOS transistors are coupled together through a low pass filter.

19. The oscillator of claim 13 wherein the second and third PMOS transistors are coupled together through a capacitor.

20. The oscillator of claim 13 further comprising a control circuit for providing a switching control circuit to the first and second switching transistors.