Quantum well graphene structure formed on a dielectric layer having a flat surface
View Patent ↗An electronic device employing a graphene layer as a charge carrier layer. The graphene layer is sandwiched between layers that are constructed of a material having a highly ordered crystalline structure and a high dielectric constant. The highly ordered crystalline structure of the layers surrounding the graphene layer has low density of charged defects that can lead to scattering of charge carriers in the graphene layer. The high dielectric constant of the layers surrounding the graphene layer also prevents charge carrier scattering by minimizing interaction between the charge carriers and the changed defects in the surrounding layers. An interracial layer constructed of a thin, non-polar, dielectric material can also be provided between the graphene layer and each of the highly ordered crystalline high dielectric constant layers to minimize charge carrier scattering in the graphene layer through remote interfacial phonons.
1. An electronic device, comprising:
an under-layer constructed of a dielectric material and having a surface with a root mean square roughness of less than 0.5 nm; and
a layer of n-graphene formed on the under-layer;
wherein the under-layer comprises HfO 2 , Al 2 O 3 , Si 3 N 4 , Y 2 O 3 , PrO, GdO, La 2 O 3 , TiO, ZrO, AlN, BN, Ta 2 O 5 , Ba x Sr (1−x) , TiO 3 , Pb x Zr (1−x) , or TiO 3 .
2. An electronic device as in claim 1 wherein further comprising an over-layer formed of a dielectric material, the layer of n-graphene being formed between the under-layer and the over-layer.
3. The electronic device as in claim 2 wherein the over-layer comprises HfO 2 , Al 2 O 3 , Si 3 N 4 , Y 2 O 3 , PrO, GdO, La 2 O 3 , TiO, ZrO, AlN, BN, Ta 2 O 5 , Ba x Sr (1−x) , TiO 3 , Pb x Zr (1−x) , or TiO 3 .
4. The electronic device as in claim 2 wherein the under-layer and over-layer each comprise HfO 2 , Al 2 O 3 , Si 3 N 4 , Y 2 O 3 , PrO, GdO, La 2 O 3 , TiO, ZrO, AlN, BN, Ta 2 O 5 , Ba x Sr (1−x) , TiO 3 , Pb x Zr (1−x) , or TiO 3 .
5. The electronic device as in claim 2 wherein the layer of n-graphene is sandwiched between and contacts each of the under-layer and over-layer.
6. The electronic device as in claim 2 wherein the under-layer and the over-layer each have a dielectric constant of at least 4.
7. The electronic device as in claim 1 wherein the over-layer has a substantially atomically flat surface.
8. The electric device as in claim 1 wherein the under-layer is constructed of a highly ordered crystalline material.
9. The electronic device as in claim 1 wherein the under-layer has a dielectric constant of at least 4.
10. An electronic device, comprising:
an under-layer formed of a dielectric material and having a root mean square surface roughness of less than 0.5 nm;
an interfacial layer formed on the under-layer; and
an n-graphene layer formed on the interfacial layer.
11. The electronic device as in claim 10 further comprising:
a second interfacial layer formed over the n-graphene layer; and
a over-layer formed over the second interfacial layer.
12. The electronic device as in claim 11 wherein the interfacial layer and the second interfacial layer are each comprise a material having a weak frequency dependence of its dielectric constant.
13. The electronic device as in claim 11 wherein each of the interfacial layers has a thickness that is not greater than 10 nm.
14. The electronic device as in claim 11 wherein the interfacial layer and second interfacial layer each comprise a self-assembled mono-layer.
15. The electronic device as in claim 11 wherein the interfacial layer and second interfacial layer each comprise 18-phenoxyoctadecyl)-trichlorsilane, octadecyltrichlorsilane, poly(a-methylstyrene), polyethylene, polypropylene or polystyrene.
16. The electronic device as in claim 10 the interfacial layer comprises a material having a weak frequency dependence of its dielectric constant.
17. The electronic device as in claim 10 wherein the interfacial layer has a thickness that is not greater than 10 nm.
18. The electronic device as in claim 10 wherein the interfacial layer comprises a self-assembled mono-layer.
19. The electronic device as in claim 10 wherein the interfacial layer comprises 18-phenoxyoctadecyl)-trichlorsilane, octadecyltrichlorsilane, poly(a-methylstyrene), polyethylene, polypropylene or polystyrene.