Low cost adjacent double error correcting code
View Patent ↗A device includes a controller configured to provide a data word and check bits for the data word to decoding logic, the decoding logic configured to generate a decoding of the data word and check bits for the data word in conformance with an H-matrix having the following properties: (a) no all 0 columns; (b) all columns are distinct; (c) no linear dependency involving three or less columns; (d) no linear dependency involving columns C i , C j , C k , C m , where m>k>j>i, where j=i+1 and m=k+1; and (e) no linear dependency involving columns C i , C j , C k , C m , where m>k>j>i, where (j=i+1 and m−k=q) or (k=j+1 and m−i=q) or (m=k+1 and j−i=q) for all integer values of q such that q>1 and q<=d, where d>=2 and d<=n−1 where n−k is a number of the check bits.
1. A device, comprising:
a controller configured to provide a data word and check bits for the data word to decoding logic;
the decoding logic configured to generate a decoding of the data word and check bits for the data word in conformance with an H-matrix having the following properties:
(a) no all 0 columns;
(b) all columns are distinct;
(c) no linear dependency involving three or less columns;
(d) no linear dependency involving columns C i , C j , C k , C m , where m>k>j>i, where j=i+1 and m=k+1; and
(e) no linear dependency involving columns C i , C j , C k , C m , where m>k>j>i, where (j=i+1 and m−k=q) or (k=j+1 and m−i=q) or (m=k+1 and j−i=q) for all integer values of q such that q>1 and q<=d, where d>=2 and d<=n−1 where n−k is a number of the check bits.
2. The device of claim 1 , the H-matrix configured to apply at least six (6) check bits to a 16-bit data word.
3. The device of claim 1 , the H-matrix configured to apply at least seven (7) check bits to a data word with 16<data bits <=32.
4. The device of claim 1 , the H-matrix configured to apply at least eight (8) check bits to a data word with 16<data bits <=32.
5. The device of claim 1 , the H-matrix configured to apply at least eight (8) check bits to a data word with 32<data bits <=64.
6. The device of claim 1 , the H-matrix configured to apply at least nine (9) check bits to a data word with 32<data bits <=64.
7. The device of claim 1 , the H-matrix configured to apply at least twelve (12) check bits to a data word with 32<data bits <=64.
8. A device, comprising:
a controller configured to provide a data word to encoding logic;
the encoding logic configured to generate an encoding of the data word in conformance with a G-matrix corresponding to a decoding H-matrix having the following properties:
(a) no all 0 columns;
(b) all columns are distinct;
(c) no linear dependency involving three or less columns;
(d) no linear dependency involving columns C i , C j , C k , C m , where m>k>j>i, such that j=i+1 and m=k+1; and
(e) no linear dependency involving columns C i , C j , C k , C m , where m>k>j>i, where m>k>j>i, where (j=i+1 and m−k=q) or (k j+1 and m−i=q) or (m=k+1 and j−i=q) for all integer values of q such that q>1 and q<=d, where d>=2 and d<=n−1 where n−k is a number of check bits for the data word.
9. The device of claim 8 , the G-matrix configured to generate at least six (6) check bits for a 16-bit data word.
10. The device of claim 8 , the G-matrix configured to generate at least seven (7) check bits for a data word with 16<data bits <=32.
11. The device of claim 8 , the G-matrix configured to generate at least eight (8) check bits for a data word with 16<data bits <=32.
12. The device of claim 8 , the G-matrix configured to generate at least eight (8) check bits for a data word with 32<data bits <=64.
13. The device of claim 8 , the H-matrix configured to generate at least nine (9) check bits for a data word with 32<data bits <=64.
14. The device of claim 8 , the H-matrix configured to generate at least twelve (12) check bits for a data word with 32<data bits <=64.
15. A memory system, comprising:
a memory controller configured to provide a data word to encoding logic;
the encoding logic configured to generate an encoding of the data word in conformance with a G-matrix corresponding to a decoding H-matrix having the following properties:
(a) no all 0 columns;
(b) all columns are distinct;
(c) no linear dependency involving three or less columns;
(d) no linear dependency involving columns C i , C j , C k , C m , where m>k>j>i, such that j=i+1 and m=k+1; and
(e) no linear dependency involving columns C i , C j , C k , C m , where m>k>j>i, where m>k>j>i, where (j=i+1 and m−k=q) or (k=j +1 and m−i=q) or (m=k+1 and j−i=q) for all integer values of q such that q>1 and q<=d, where d>=2 and d<=n−1 where n−k is a number of check bits for the data word; and
the memory controller configured to provide the encoding of the data word to decoding logic based on the H-matrix.
16. The memory system of claim 15 , further comprising:
the decoding logic comprising syndrome detection logic to detect matches of any n−1 adjacent double error syndromes for the encoding of the data word, and upon detecting a match to output an indication of a double adjacent error and corresponding bit positions of the double adjacent error.
17. The memory system of claim 15 , the H-matrix configured to apply at least six (6) check bits to a 16-bit data word.
18. The memory system of claim 15 , the H-matrix configured to apply at least seven (7) check bits to a data word with 16<data bits <=32.
19. The memory system of claim 15 , the H-matrix configured to apply at least eight (8) check bits to a data word with 16<data bits <=32.
20. The memory system of claim 15 , the H-matrix configured to apply at least eight (8) check bits to a data word with 32<data bits <=64.