Semiconductor device and fabricating method thereof
A semiconductor device includes: a memory cell transistor which has a floating gate, a control gate, and a source and a drain formed in a semiconductor substrate on both sides of the floating gate via a channel area; and a selecting transistor which has a select gate and a source and a drain formed in the semiconductor substrate on both sides of the select gate, wherein the source of the selecting transistor is connected to the drain of the memory cell transistor, the source of the memory cell transistor has an N-type first impurity diffusion layer, an N-type second impurity diffusion layer deeper than the first impurity diffusion layer, and an N-type third impurity diffusion layer which is shallower than the second impurity diffusion layer, and an impurity density of the second impurity diffusion layer is lower than that of the third impurity diffusion layer.
1. A method for fabricating a semiconductor device, comprising:
forming a first conductive film over a semiconductor substrate via a first insulating film;
forming a second conductive film over the first conductive film via a second insulating film;
patterning the first conductive film, the second insulating film, and the second conductive film so as to form a laminated body having a floating gate of the first conductive film and a control gate of the second conductive film formed over the floating gate via the second insulating film, and to form a select gate of the first conductive film in parallel with the floating gate;
forming a first P-type impurity diffusion layer in the semiconductor substrate on an area to be a source of a memory cell transistor having the floating gate and the control gate, so as to extend into an area below the floating gate;
forming a first N-type impurity diffusion layer which is deeper than the first P-type impurity diffusion layer, in the semiconductor substrate on the area to be the source of the memory cell;
forming a first side wall insulating film on a side wall portion of the laminated body and a side wall portion of the select gate;
patterning the first conductive film over a peripheral circuit area of the semiconductor substrate to form a gate electrode of a high-withstand voltage transistor;
forming a second N-type impurity diffusion layer in the semiconductor substrate on the area to be the source of the memory cell transistor and an N-type low-density diffusion layer in the semiconductor substrate on both sides of the gate electrode of a high-withstand voltage transistor, the second N-type impurity diffusion layer is deeper than the first N-type impurity diffusion layer, a width of the second N-type impurity diffusion layer is narrower than a width of the first N-type impurity diffusion layer;
forming a second side wall insulating film on the side wall portion of the laminated body and the side wall portion of the select gate which are formed with the first side wall insulating film; and
forming a third N-type impurity diffusion layer in the second N-type impurity diffusion layer, which is shallower than the second N-type impurity diffusion layer, a width of the third N-type impurity diffusion layer is narrower than the width of the second N-type impurity diffusion layer, and an impurity concentration of the third N-type impurity diffusion layer is higher than an impurity concentration of the second N-type impurity diffusion layer.
2. The method according to claim 1 , wherein
the end portion of the first N-type impurity diffusion layer on the floating gate side is positioned within an area below the floating gate.
3. The method according to claim 1 , wherein
the impurity concentration in a portion of the second N-type impurity diffusion layer deeper than the third N-type impurity diffusion layer is lower than a impurity concentration in the end portion of the first N-type impurity diffusion layer on the floating gate side.
4. The method according to claim 1 , wherein when forming the first N-type impurity diffusion layer, a fifth N-type impurity diffusion layer is formed in the semiconductor substrate on an area to be a drain of the memory cell transistor and a source of the selecting transistor having the select gate, and a sixth N-type impurity diffusion layer is formed in the semiconductor substrate on an area to be a drain of the selecting transistor together with the first N-type impurity diffusion layer.