Fabrication method of semiconductor device and fabrication method of dynamic threshold transistor

1. A method of fabricating a semiconductor device, comprising:

forming a gate insulation film on a silicon substrate defined with a device region by a device isolation trench and a gate electrode on said gate insulation film;

forming a source extension region and a drain extension region in said silicon substrate portion respectively at a first side and a second side opposite to said first side of said gate electrode by introducing an impurity element of a first conductivity type;

forming sidewall insulation films respectively on a sidewall surface at said first side and on a sidewall surface at said second side of said gate electrode;

etching said silicon substrate while using said sidewall insulation films as a mask to form first and second trenches respectively at said first side and said second side of said gate electrode at respective outer sides of said sidewall insulation films as viewed from said gate electrode;

forming a first semiconductor layer which has etching selectivity against silicon in said first and second trenches and a silicon layer on said first semiconductor layer in said first and second trenches by consecutively and epitaxially growing;

exposing, after forming said first semiconductor layer and said silicon layer, said first semiconductor layer by causing a recession in a device isolation insulation film constituting said device isolation region of STI type;

removing said first semiconductor layer selectively to form a void between said silicon substrate and said silicon layer;

forming a buried insulation film in at least a part of said void,

forming a source region and a drain region by introducing an impurity element of said first conductivity type into said silicon layer respectively at said first side and said second side of said gate electrode.

2. The method as claimed in claim 1 , wherein said forming said source region and said drain region includes performing an ion implantation of said impurity element of said first conductivity type while using said sidewall insulation films as a mask.

3. The method as claimed in claim 1 , wherein said forming said source region and said drain region comprises: removing said sidewall insulation films; forming second sidewall insulation films respectively on said sidewall surfaces at said first side and said second side of said gate electrode; and introducing said impurity element of said first conductivity while using said second sidewall insulation films as a mask.

4. The method of fabricating a semiconductor device as claimed in claim 1 , further comprising:

after forming said buried insulation film, selectively removing said silicon layer selectively with regard to said buried insulation film; and growing a second semiconductor layer which has a lattice constant different from a lattice constant of silicon on said buried insulation film epitaxially with regard to said substrate portion to form a strained region.

5. The method as claimed in claim 4 , wherein said semiconductor device comprises a p-channel MOS transistor and said second semiconductor layer includes a SiGe mixed crystal layer.

6. The method as claimed in claim 5 , further comprising forming a compressive stressor film on said silicon substrate and said second semiconductor layer.

7. The method as claimed in claim 4 , wherein said semiconductor device comprises a n-channel MOS transistor and said second semiconductor layer includes a SiC mixed crystal layer.

8. The method as claimed in claim 7 , wherein further comprising forming a tensile stressor film on said silicon substrate and said second semiconductor layer.

9. A method of fabricating a semiconductor device, comprising:

forming a gate insulation film on a silicon substrate defined with a device region by a device isolation trench of STI type and a gate electrode on said gate insulation film;

forming a source extension region and a drain extension region in said silicon substrate portion respectively at a first side and a second side opposite to said first side of said gate electrode by introducing an impurity element of a first conductivity type;

forming sidewall insulation films respectively on a sidewall surface at said first side and on a sidewall surface at said second side of said gate electrode;

etching said silicon substrate while using said sidewall insulation films as a mask to form first and second trenches respectively at said first side and said second side of said gate electrode at respective outer sides of said sidewall insulation films as viewed from said gate electrode;

removing a part of a device isolation insulation film constituting said device isolation region;

after removing a part of a device isolation insulation film, forming a semiconductor layer which has etching selectivity against silicon in said first and second trenches and a silicon layer on said semiconductor layer in said first and second trenches consecutively and such that said semiconductor layer is exposed at a device isolation trench constituting said device isolation region;

removing said semiconductor layer selectively to form a void between said silicon substrate and said silicon layer;

forming a buried insulation film in at least a part of said void; and

forming a source region and a drain region by introducing an impurity element of said first conductivity type into said silicon layer constituting said stacked structure respectively at said first side and said second side of said gate electrode.