An arithmetic operation circuit provided in a delta-sigma modulator of a delta-sigma A/D converter includes two reference capacitors which are respectively provided at a positive side input node and a negative side input node of an operational amplifier. When a signal corresponding to an output of the modulator is added or subtracted to or from an input signal, the amount of charge added to the input node of the operational amplifier is made to be always the same regardless of the reference voltage by complementarily switching the connection of the reference capacitors at the positive side input node and the negative side input node, and thereby the potential of the input node of the operational amplifier is made to converge to the common mode potential of the circuit.
1. An A/D converter comprising:
a modulator configured to perform delta-sigma modulation of a differential analog signal; and
a decimation filter configured to generate digital data on the basis of an output of the modulator,
wherein the modulator comprises at least one arithmetic operation circuit configured to alternately repeat a sampling state and an arithmetic operation state including:
a first capacitor and a second capacitor each of which samples an input signal;
a third capacitor and a fourth capacitor each of which has a first electrode connected to a first electrode of the first capacitor and configured to perform sampling of a first reference voltage or a second reference voltage different from the first reference voltage;
a fifth capacitor and a sixth capacitor each of which has a first electrode connected to a first electrode of the second capacitor and configured to perform sampling of the first reference voltage or the second reference voltage; and
the arithmetic operator configured to obtain a first addition or subtraction result by performing addition or subtraction between charge sampled by the first capacitor and charge sampled by the third capacitor and the fourth capacitor, and configured to obtain a second addition or subtraction result by performing addition or subtraction between charge sampled by the second capacitor and charge sampled by the fifth capacitor and the sixth capacitor, and thereby integrates the first addition or subtraction result to output a first integration result, and integrates the second addition or subtraction result to output a second integration result,
wherein in an addition state of the arithmetic operation state, a second electrode of each of the third capacitor and the fourth capacitor is connected to the first reference voltage, and a second electrode of each of the fifth capacitor and the sixth capacitor is connected to the second reference voltage,
wherein in a subtraction state of the arithmetic operation state, the second electrode of each of the third capacitor and the fourth capacitor is connected to the second reference voltage, and the second electrode of each of the fifth capacitor and the sixth capacitor is connected to the first reference voltage, and
wherein in the sampling state, the second electrode of each of the third capacitor and the sixth capacitor is connected to the first reference voltage, and the second electrode of each of the fourth capacitor and the fifth capacitor is connected to the second reference voltage.
2. The A/D converter according to claim 1 that alternately repeats
a first state in which the second electrode of one of the third capacitor and the fourth capacitor is connected to the first reference voltage, the second electrode of the other of the third capacitor and the fourth capacitor is connected to the second reference voltage, the second electrode of one of the fifth capacitor and the sixth capacitor is connected to the first reference voltage, and the second electrode of the other of the fifth capacitor and the sixth capacitor is connected to the second reference voltage, and
a second state in which, according to a feedback signal based on the output of the modulator, the second electrode of each of the third capacitor and the fourth capacitor is connected to the first reference voltage, and also the second electrode of each of the fifth capacitor and the sixth capacitor is connected to the second reference voltage, or the second electrode of each of the third capacitor and the fourth capacitor is connected to the second reference voltage, and also the second electrode of each of the fifth capacitor and the sixth capacitor is connected to the first reference voltage.
3. The A/D converter according to claim 2 , wherein the modulator includes a plurality of the arithmetic operation circuits; and
when one of the plurality of the arithmetic operation circuits arranged in series is set in the first state, the other arithmetic operation circuits is set in the second state.
4. An arithmetic operator of a delta-sigma type A/D converter comprising,
a fully differential operational amplifier including a negative side input node which is connected, via a first switch, to a first electrode of each of a first capacitor, a third capacitor, and a fourth capacitor, and a positive side input node which is connected, via a second switch, to a first electrode of each of the second capacitor, a fifth capacitor, and a sixth capacitor;
a seventh capacitor which is connected between the negative side input node and a positive side output node of the fully differential operational amplifier;
an eighth capacitor which is connected between the positive side input node and a negative side output node of the fully differential operational amplifier;
a common mode voltage node independent of a reference voltage, from a plurality of references, and the common mode potential of the inputted differential signal is connected with a first switch to the first electrode of the first capacitor, the third capacitor, and the fourth capacitor;
connected with a second switch to the first electrode of the second capacitor, the fifth capacitor, and the sixth capacitor; coupled with a third switch to a second electrode of the first capacitor; and
coupled with a fourth switch to a second electrode of the second capacitor, and
an arithmetic operation circuit configured to alternately repeat a sampling state and an arithmetic operation state,
wherein in the sampling state, a second electrode of each of the third capacitor and the sixth capacitor is connected to a first reference voltage, and a second, electrode of each of the fourth capacitor and the fifth capacitor is connected to a second reference voltage,
wherein in a case where addition is performed in the arithmetic operation state, the second electrode of each of the third capacitor and the fourth capacitor is connected to the first reference voltage, and the second electrode of each of the fifth capacitor and the sixth capacitor is connected to the second reference voltage; and
wherein in a case where subtraction is performed in the arithmetic operation state, the second electrode of each of the third capacitor and the fourth capacitor is connected to the second reference voltage, and the second electrode of each of the fifth capacitor and the sixth capacitor is connected to the first reference voltage.
5. An arithmetic operator of a delta-sigma type A/D converter comprising,
a modulator configured to perform delta-sigma modulation of a differential analog signal; and
a decimation filter configured to generate digital data on basis of an output of the modulator,
wherein the modulator comprises at least one arithmetic operation circuit that alternately repeats a sampling state and an arithmetic operation state including:
a first capacitor and a second capacitor each of which samples an input signal;
a third capacitor and a fourth capacitor each of which has a first electrode connected to a first electrode of the first capacitor and, configured to perform sampling of a first reference voltage or a second reference voltage different from the first reference voltage; and
a fifth capacitor and a sixth capacitor each of which has a first electrode connected to a first electrode of the second capacitor and configured to perform sampling of the first reference voltage or the second reference voltage;
a fully differential operational amplifier including a negative side input node which is connected to the first electrode of each of the first capacitor, the third capacitor, and the fourth capacitor, and a positive side input node which is connected to the first electrode of each of the second capacitor, the fifth capacitor, and the sixth capacitor;
a first switch and a seventh capacitor which are connected in series between the negative side input node and a positive side output node of the fully differential operational amplifier;
a second switch which is connected between the negative side input node and the positive side output node of the fully differential operational amplifier;
a third switch and an eighth capacitor which are connected in series between the positive side input node and a negative side output node of the fully differential operational amplifier; and
a fourth switch which is connected between the positive side input node and the negative side output node of the fully differential operational amplifier.
6. An arithmetic operator of a delta-sigma type A/D converter comprising,
a modulator configured to performs delta-sigma modulation of a differential analog signal; and
a decimation filter configured to generate digital data on basis of an output of the modulator,
wherein the modulator comprises at least one arithmetic operation circuit that alternately repeats a sampling state and an arithmetic operation state including:
a first capacitor and a second capacitor each of which are configured to sample an input signal;
a third capacitor and a fourth capacitor each of which has a first electrode connected to a first electrode of the first capacitor and configured to perform sampling of a first reference voltage or a second reference voltage different from the first reference voltage; and
a fifth capacitor and a sixth capacitor each of which has a first electrode connected to a first electrode of the second capacitor and configured to perform sampling of the first reference voltage or the second reference voltage;
a fully differential operational amplifier including a negative side input node which is connected to the first electrode of each of the first capacitor, the third capacitor, and the fourth capacitor, and a positive side input node which is connected to the the electrode of each of the second capacitor, the fifth capacitor, and the sixth capacitor;
a third switch and a ninth capacitor which are connected in series between the negative side input node and a positive side output node of the fully differential operational amplifier;
a fourth switch which is connected between the negative side input node and the positive side output node of the fully differential operational amplifier;
a fifth switch and a tenth capacitor which are connected in series between the positive side input node and a negative side output node of the fully differential operational amplifier; and
a sixth switch which is connected between the positive side input node and the negative side output node of the fully differential operational amplifier.
7. An arithmetic operator of a delta-sigma type A/D converter comprising a plurality of arithmetic operation circuits, the arithmetic operator of the plurality of the arithmetic operation circuits of a first stage includes:
a modulator configured to performs delta sigma modulation of a differential analog signal; and
a decimation filter configured to generate digital data on basis of an output of the modulator,
wherein the modulator comprises at least one arithmetic operation circuit that alternately repeats a sampling state and an arithmetic operation state including:
a first capacitor and a second capacitor each of which samples an input signal;
a third capacitor and a fourth capacitor each of which has a first electrode connected to a first electrode of the first capacitor and configured to perform sampling of a first reference voltage or a second reference voltage different from the first reference voltage;
a fifth capacitor and a sixth capacitor each of which has a first electrode connected to a first electrode of the second capacitor and configured to perform sampling of the first reference voltage or the second reference voltage;
a fully differential operational amplifier including a negative side input node which is connected to the first electrode of each of the first capacitor, the third capacitor, and the fourth capacitor, and a positive side input node which is connected to the first electrode of each of the second capacitor, the fifth capacitor, and the sixth capacitor;
a first switch and a seventh capacitor which are connected in series between the negative side input node and a positive side output node of the fully differential operational amplifier;
a second switch which is connected between the negative side input node and the positive side output node of the fully differential operational amplifier;
a third switch and an eighth capacitor which are connected in series between the positive side input node and a negative side output node of the fully differential operational amplifier; and
a fourth switch which is connected between the positive side input node and the negative side output node of the fully differential operational amplifier, and the arithmetic operator of the arithmetic operation circuit of each of stages subsequent to the first stage includes:
a fully differential operational amplifier comprising a negative side input node which is connected, via a fifth switch, to the first electrode of each of the first capacitor, the third capacitor, and the fourth capacitor, and a positive side input node which is connected, via a sixth switch, to the first electrode of each of the second capacitor, the fifth capacitor, and the sixth capacitor;
a ninth capacitor which is connected between the negative side input node and a positive side output node of the fully differential operational amplifier; and
a tenth capacitor which is connected between the positive side input node and a negative side output node of the fully differential operational amplifier.
8. The A/D converter according to claim 1 ,
wherein the first reference voltage is a ground voltage, and the second reference voltage is a voltage to be referred to.
9. The A/D converter according to claim 4 , wherein:
the first capacitor and the second capacitor each of which samples an input signal;
the first electrode of the third and the forth capacitor connected to the first electrode of the first capacitor and performs sampling of the first reference voltage or the second reference voltage different from the first reference voltage;
the first electrode of the fifth and the sixth capacitor connected to the first electrode of the second capacitor and performs sampling of the first reference voltage or the second reference voltage; and
the arithmetic operator configured to obtain a first addition or subtraction result by performing addition or subtraction between charge sampled by the first capacitor and charge sampled by the third capacitor and the fourth capacitor, and configured to obtain a second addition or subtraction result by performing addition or subtraction between charge sampled by the second capacitor and charge sampled by the fifth capacitor and the sixth capacitor, and thereby integrates the first addition or subtraction result to output a first integration result, and integrates the second addition or subtraction result to output a second integration result.
10. The A/D converter according to claim 4 that alternately repeats
a first state in which the second electrode of one of the third capacitor and the fourth capacitor is connected to the first reference voltage, the second electrode of the other of the third capacitor and the fourth capacitor is connected to the second reference voltage, the second electrode of one of the fifth capacitor and the sixth capacitor is connected to the first reference voltage, and the second electrode of the other of the fifth capacitor and the sixth capacitor is connected to the second reference voltage, and
a second state in which, according to a feedback signal based on the output of the modulator, the second electrode of each of the third capacitor and the fourth capacitor is connected to the first reference voltage, and also the second electrode of each of the fifth capacitor and the sixth capacitor is connected to the second reference voltage, or the second electrode of each of the third capacitor and the fourth capacitor is connected to the second reference voltage, and also the second electrode of each of the fifth capacitor and the sixth capacitor is connected to the first reference voltage.
11. The A/D converter according to claim 10 , wherein the modulator includes a plurality of the arithmetic operation circuits; and
when one of the plurality of the arithmetic operation circuits arranged in series is set in the first state, the other arithmetic operation circuits is set in the second state.
12. The A/D converter according to claim 4 , further comprising the first reference voltage and the second reference voltage, wherein the first reference voltage is a ground voltage and the second reference voltage is a voltage to be referred to.
13. The A/D converter according to claim 5 , wherein:
the first capacitor and the second capacitor each of which samples an input signal;
the first electrode of the third and the fourth capacitor connected to the first electrode of the first capacitor and performs sampling of the first reference voltage or the second reference voltage different from the first reference voltage;
the first electrode of the fifth and the sixth capacitor connected to the first electrode of the second capacitor and performs sampling of the first reference voltage or the second reference voltage; and
the arithmetic operator configured to obtain a first addition or subtraction result by performing addition or subtraction between charge sampled by the first capacitor and charge sampled by the third capacitor and the fourth capacitor, and configured to obtain a second addition or subtraction result by performing addition or subtraction between charge sampled by the second capacitor and charge sampled by the fifth capacitor and the sixth capacitor, and thereby integrates the first addition or subtraction result to output a first integration result, and integrates the second addition or subtraction result to output a second integration result.
14. The A/D converter according to claim 5 that alternately repeats
a first state in which a second electrode of one of the third capacitor and the fourth capacitor is connected to the first reference voltage, the second electrode of the other of the third capacitor and the fourth capacitor is connected to the second reference voltage, a second electrode of one of the fifth capacitor and the sixth capacitor is connected to the first reference voltage, and the second electrode of the other of the fifth capacitor and the sixth capacitor is connected to the second reference voltage, and
a second state in which, according to a feedback signal based on the output of the modulator, the second electrode of each of the third capacitor and the fourth capacitor is connected to the first reference voltage, and also the second electrode of each of the fifth capacitor and the sixth capacitor is connected to the second reference voltage, or the second electrode of each of the third capacitor and the fourth capacitor is connected to the second reference voltage, and also the second electrode of each of the fifth capacitor and the sixth capacitor is connected to the first reference voltage.
15. The A/D converter according to claim 14 , wherein the modulator includes a plurality of the arithmetic operation circuits; and
when one of the plurality of the arithmetic operation circuits arranged in series is set in the first state, the other arithmetic operation circuits is set in the second state.
16. The A/D converter according to claim 5 , wherein:
the arithmetic operation circuit alternately repeats a sampling state and an arithmetic operation state;
in the sampling state, a second electrode of each of the third capacitor and the sixth capacitor is connected to the first reference voltage, and a second electrode of each of the fourth capacitor and the fifth capacitor is connected to the second reference voltage;
in the case where addition is performed in the arithmetic operation state, the second electrode of each of the third capacitor and the fourth capacitor is connected to the first reference voltage, and the second electrode of each of the fifth capacitor and the sixth capacitor is connected to the second reference voltage; and
in the case where subtraction is performed in the arithmetic operation state, the second electrode of each of the third capacitor and the fourth capacitor is connected to the second reference voltage, and the second electrode of each of the fifth capacitor and the sixth capacitor is connected to the first reference voltage.
17. The A/D converter according to claim 5 , further comprising the first reference voltage and the second reference voltage, wherein the first reference voltage is a ground voltage and the second reference voltage is a voltage to be referred to.
18. The A/D converter according to claim 6 , wherein:
the first capacitor and the second capacitor each of which samples an input signal;
the first electrode of the third and the fourth capacitor connected to the first electrode of the first capacitor and performs sampling of the first reference voltage or the second reference voltage different from the first reference voltage;
the first electrode of the fifth and the sixth capacitor connected to the first electrode of the second capacitor and performs sampling of the first reference voltage or the second reference voltage; and
the arithmetic operator configured to obtain a first addition or subtraction result by performing addition or subtraction between charge sampled by the first capacitor and charge sampled by the third capacitor and the fourth capacitor, and configured to obtain a second addition or subtraction result by performing addition or subtraction between charge sampled by the second capacitor and charge sampled by the fifth capacitor and the sixth capacitor, and thereby integrates the first addition or subtraction result to output a first integration result, and integrates the second addition or subtraction result to output a second integration result.
19. The A/D converter according to claim 6 that alternately repeats
a first state in which a second electrode of one of the third capacitor and the fourth capacitor is connected to the first reference voltage, the second electrode of the other of the third capacitor and the fourth capacitor is connected to the second reference voltage, a second electrode of one of the fifth capacitor and the sixth capacitor is connected to the first reference voltage, and the second electrode of the other of the fifth capacitor and the sixth capacitor is connected to the second reference voltage, and
a second state in which, according to a feedback signal based on the output of the modulator, the second electrode of each of the third capacitor and the fourth capacitor is connected to the first reference voltage, and also the second electrode of each of the fifth capacitor and the sixth capacitor is connected to the second reference voltage, or the second electrode of each of the third capacitor and the fourth capacitor is connected to the second reference voltage, and also the second electrode of each of the fifth capacitor and the sixth capacitor is connected to the first reference voltage.
20. The A/D converter according to claim 19 , wherein the modulator includes a plurality of the arithmetic operation circuits; and
when one of the plurality of the arithmetic operation circuits arranged in series is set in the first state, the other arithmetic operation circuits is set in the second state.
21. The A/D converter according to claim 6 , wherein:
the arithmetic operation circuit alternately repeats a sampling state and an arithmetic operation state;
in the sampling state, a second electrode of each of the third capacitor and the sixth capacitor is connected to the first reference voltage, and a second electrode of each of the fourth capacitor and the fifth capacitor is connected to the second reference voltage;
in the case where addition is performed in the arithmetic operation state, the second electrode of each of the third capacitor and the fourth capacitor is connected to the first reference voltage, and the second electrode of each of the fifth capacitor and the sixth capacitor is connected to the second reference voltage; and
in the case where subtraction is performed in the arithmetic operation state, the second electrode of each of the third capacitor and the fourth capacitor is connected to the second reference voltage, and the second electrode of each of the fifth capacitor and the sixth capacitor is connected to the first reference voltage.
22. The A/D converter according to claim 6 , further comprising the first reference voltage and the second reference voltage, wherein the first reference voltage is a ground voltage and the second reference voltage is a voltage to be referred to.
23. The A/D converter according to claim 7 , wherein:
the first capacitor and the second capacitor each of which samples an input signal;
the first electrode of the third and the fourth capacitor connected to the first electrode of the first capacitor and performs sampling of the first reference voltage or the second reference voltage different from the first reference voltage;
the first electrode of the fifth and the sixth capacitor connected to the first electrode of the second capacitor and performs sampling of the first reference voltage or the second reference voltage; and
the arithmetic operator which configured to obtain a first addition or subtraction result by performing addition or subtraction between charge sampled by the first capacitor and charge sampled by the third capacitor and the fourth capacitor, and configured to obtain a second addition or subtraction result by performing addition or subtraction between charge sampled by the second capacitor and charge sampled by the fifth capacitor and
the sixth capacitor, and thereby integrates the first addition or subtraction result to output a first integration result, and integrates the second addition or subtraction result to output a second integration result.
24. The A/D converter according to claim 7 that alternately repeats a first state in which a second electrode of one of the third capacitor and the fourth capacitor is connected to the first reference voltage, the second electrode of the other of the third capacitor and the fourth capacitor is connected to the second reference voltage, a second electrode of one of the fifth capacitor and the sixth capacitor is connected to the first reference voltage, and the second electrode of the other of the fifth capacitor and the sixth capacitor is connected to the second reference voltage, and
a second state in which, according to a feedback signal based on the output of the modulator, the second electrode of each of the third capacitor and the fourth capacitor is connected to the first reference voltage, and also the second electrode of each of the fifth capacitor and the sixth capacitor is connected to the second reference voltage, or the second electrode of each of the third capacitor and the fourth capacitor is connected to the second reference voltage, and also the second electrode of each of the fifth capacitor and the sixth capacitor is connected to the first reference voltage.
25. The A/D converter according to claim 24 , wherein the modulator includes the plurality of the arithmetic operation circuits; and
when one of the plurality of the arithmetic operation circuits arranged in series is set in the first state, the other arithmetic operation circuits is set in the second state.
26. The A/D converter according to claim 7 , wherein:
the arithmetic operation circuit alternately repeats a sampling state and an arithmetic operation state;
in the sampling state, a second electrode of each of the third capacitor and the sixth capacitor is connected to the first reference voltage, and a second electrode of each of the fourth capacitor and the fifth capacitor is connected to the second reference voltage;
in the case where addition is performed in the arithmetic operation state, the second electrode of each of the third capacitor and the fourth capacitor is connected to the first reference voltage, and the second electrode of each of the fifth capacitor and the sixth capacitor is connected to the second reference voltage; and
in the case where subtraction is performed in the arithmetic operation state, the second electrode of each of the third capacitor and the fourth capacitor is connected to the second reference voltage, and the second electrode of each of the fifth capacitor and the sixth capacitor is connected to the first reference voltage.
27. The A/D converter according to claim 7 , further comprising the first reference voltage and the second reference voltage, wherein the first reference voltage is a ground voltage and the second reference voltage is a voltage to be referred to.