IP Library Granted Patent US 9,024,710
Granted Patent B2
US 9,024,710 · App. 13/560,893 · Granted May 5, 2015

Low-voltage active inductor

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Quick Facts
Patent No.
US 9,024,710
App. No.
13/560,893
Granted
May 5, 2015
Kind
B2
Abstract

An active inductor circuit includes a field-effect transistor having a first source/drain adapted for connection with a first voltage source, a capacitor coupled between the first voltage source and a gate of the field-effect transistor, a resistor coupled between a second source/drain of the field-effect transistor and the gate of the field-effect transistor, and a current source coupled with the gate of the field-effect transistor. A voltage headroom of the active inductor circuit is controlled as a function of at least one of a magnitude of current generated by the current source and a resistance of the resistor.

Claims (40)

1. An active inductor circuit, comprising:

a field-effect transistor having a first source/drain adapted for connection with a first voltage source;

a capacitor coupled between the first voltage source and a gate of the field-effect transistor;

a resistor coupled between a second source/drain of the field-effect transistor and the gate of the field-effect transistor; and

a current source coupled between the gate of the field-effect transistor and a second voltage source, a voltage headroom of the active inductor circuit being controlled as a function of at least one of a magnitude of current generated by the current source and a resistance of the resistor.

2. The active inductor circuit of claim 1 , wherein the current source comprises a programmable current source, an output current generated by the programmable current source being controlled as a function of at least a first control signal.

3. The active inductor circuit of claim 2 , wherein the programmable current source is adapted to receive a plurality of control signals and comprises a plurality of current segments, each of the respective current segments being selectable as a function of a corresponding one of the control signals.

4. The active inductor circuit of claim 3 , wherein each of at least a subset of the plurality of current segments comprises a transistor and a switching element connected with the transistor and adapted to receive the corresponding one of the control signals.

5. The active inductor circuit of claim 3 , wherein respective currents generated in at least a subset of the current segments are binary weighted relative to one another.

6. The active inductor circuit of claim 2 , wherein the programmable current source comprises a bias circuit, operative to generate a reference current, and a plurality of current segments connected with the bias circuit in a current mirror configuration.

7. The active inductor circuit of claim 6 , wherein a current generated in a given one of the current segments is a function of a ratio of a size of a transistor in the bias circuit to a size of a transistor in the given current segment.

8. The active inductor circuit of claim 1 , wherein the active inductor circuit forms an equivalent passive inductor having a first terminal coupled with the first voltage source and a second terminal formed at the second source/drain of the field-effect transistor.

9. The active inductor circuit of claim 8 , wherein an inductance, L, of the equivalent passive inductor is expressed as

L

=

c

·

r

g

m

,

where g m is a transconductance of the field-effect transistor, r is a resistance of the resistor, and c is a capacitance of the capacitor.

10. The active inductor circuit of claim 1 , wherein the field-effect transistor comprises a PFET device having a source adapted for connection with the first voltage source, a drain connected with a first terminal of the resistor, and a gate connected with a second terminal of the resistor and a first terminal of the capacitor.

11. The active inductor circuit of claim 10 , wherein the first voltage source is a voltage supply of the active inductor circuit and the second voltage source is a voltage return of the active inductor circuit.

12. The active inductor circuit of claim 1 , wherein the field-effect transistor comprises an NFET device having a source adapted for connection with the first voltage source, a drain connected with a first terminal of the resistor, and a gate connected with a second terminal of the resistor and a first terminal of the capacitor.

13. The active inductor circuit of claim 12 , wherein the first voltage source is a voltage return of the active inductor circuit and the second voltage source is a voltage supply of the active inductor circuit.

14. The active inductor circuit of claim 1 , wherein a first terminal of the current source is connected with the gate of the field-effect transistor and a second terminal of the current source is adapted for connection with the second voltage source.

15. The active inductor circuit of claim 1 , wherein a resistance of the resistor is set to a prescribed value and the voltage headroom of the active inductor circuit is controlled as a function of the magnitude of current generated by the current source.

16. The active inductor circuit of claim 1 , wherein the resistor comprises a programmable resistor adapted to receive at least one control signal, a resistance of the programmable resistor being controlled as a function of the at least one control signal.

17. The active inductor circuit of claim 1 , wherein the active inductor circuit is fabricated in at least one integrated circuit.

18. An electronic system, comprising:

at least one integrated circuit, the integrated circuit comprising at least one active inductor circuit, the at least one active inductor comprising:

a field-effect transistor having a first source/drain adapted for connection with a first voltage source;

a capacitor coupled between the first voltage source and a gate of the field-effect transistor;

a resistor coupled between a second source/drain of the field-effect transistor and the gate of the field-effect transistor; and

a current source coupled between the gate of the field-effect transistor and a second voltage source, a voltage headroom of the active inductor circuit being controlled as a function of at least one of a magnitude of current generated by the current source and a resistance of the resistor.

19. The system of claim 18 , wherein the at least one active inductor circuit forms an equivalent passive inductor having a first terminal coupled with the first voltage source and a second terminal formed at the second source/drain of the field-effect transistor.

20. The system of claim 18 , wherein the field-effect transistor comprises a PFET device having a source adapted for connection with the first voltage source, a drain connected with a first terminal of the resistor, and a gate connected with a second terminal of the resistor and a first terminal of the capacitor.

21. The system of claim 18 , wherein the field-effect transistor comprises an NFET device having a source adapted for connection with the first voltage source, a drain connected with a first terminal of the resistor, and a gate connected with a second terminal of the resistor and a first terminal of the capacitor.

22. The system of claim 18 , wherein at least a portion of the system is fabricated in at least one integrated circuit.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE OF THE MERGER PREVIOUSLY RECORDED ON REEL 047642 FRAME 0417. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT, Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048521/0395 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047642/0417 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2012
From: KIMURA, HIROSHI; NARAYAN, RAM S.; SINHA, ASHUTOSH K.
To: LSI CORPORATION
Reel/Frame 028662/0661 →