SYSTEM AND METHOD FOR GENERATING PHYSICAL DETERMINISTIC BOUNDARY INTERCONNECT FEATURES FOR DUAL PATTERNING TECHNOLOGIES
One aspect provides a system for generating a layout for dual patterning technologies. In one embodiment, the system includes: (1) a deterministic boundary interconnect feature generator configured to generate a deterministic boundary interconnect feature for a cell based on at least one dual patterning design rule; and (2) cell placement and interconnect routing tools associated with the deterministic boundary interconnect feature generator and configured to place the deterministic boundary interconnect feature.
1 . A system for generating a layout for dual patterning technologies, comprising:
a deterministic boundary interconnect feature generator configured to generate a deterministic boundary interconnect feature for a cell based on at least one dual patterning design rule; and
cell placement and interconnect routing tools associated with said deterministic boundary interconnect feature generator and configured to place said deterministic boundary interconnect feature;
wherein said deterministic boundary interconnect feature is a physical feature formed of one or more conductive materials that is defined and laid out using said at least one dual patterning design rule.
2 . The system as recited in claim 1 , wherein said deterministic boundary interconnect feature generator is further configured to generate a family of deterministic boundary interconnect features using a same number of interconnect layers.
3 . The system as recited in claim 2 , wherein said interconnect layers are limited to dual patterning layers.
4 . The system as recited in claim 1 , wherein said deterministic boundary interconnect feature is configured to be connected to a power rail of an integrated circuit.
5 . The system as recited in claim 1 , wherein said deterministic boundary interconnect feature is configured to be used in a capacitor.
6 . The system as recited in claim 1 , wherein said deterministic boundary interconnect feature is one of a side-cell deterministic boundary interconnect feature and a U-shaped deterministic boundary interconnect feature and corresponds to one of an I/O buffer cell and an I/O support cell.
7 . The system as recited in claim 1 , wherein said deterministic boundary interconnect feature is a full-ring deterministic boundary interconnect feature and corresponds to a core block cell.
8 . A method of generating a layout for dual patterning technologies, comprising:
generating a deterministic boundary interconnect feature for a cell based on at least one dual patterning design rule; and
placing said deterministic boundary interconnect feature;
wherein said deterministic boundary interconnect feature is a physical feature formed of one or more conductive materials that is defined and laid out using said at least one dual patterning design rule.
9 . The method as recited in claim 8 , further comprising further generating a family of deterministic boundary interconnect features using a same number of interconnect layers.
10 . The method as recited in claim 9 , wherein said interconnect layers are limited to dual patterning layers.
11 . The method as recited in claim 8 , wherein said deterministic boundary interconnect feature is configured to be connected to a power rail of an integrated circuit.
12 . The method as recited in claim 8 , wherein said deterministic boundary interconnect feature is configured to be used in a capacitor.
13 . The method as recited in claim 8 , wherein said deterministic boundary interconnect feature is one of a side-cell deterministic boundary interconnect feature and a U-shaped deterministic boundary interconnect feature and corresponds to one of an I/O buffer cell and an I/O support cell.
14 . The method as recited in claim 8 , wherein said deterministic boundary interconnect feature is a full-ring deterministic boundary interconnect feature and corresponds to a core block cell.
15 . A computer-readable storage medium containing program instructions for designing and implementing a circuit using mixed cell libraries, execution of said program instructions by one or more processors of a computer system causing said one or more processors to:
generate a deterministic boundary interconnect feature for a cell based on at least one dual patterning design rule; and
place said deterministic boundary interconnect feature;
wherein said deterministic boundary interconnect feature is a physical feature formed of one or more conductive materials that is defined and laid out using said at least one dual patterning design rule.
16 . The computer-readable storage medium as recited in claim 15 , wherein said deterministic boundary interconnect feature generator generates a family of deterministic boundary interconnect features using a same number of interconnect layers.
17 . The computer-readable storage medium as recited in claim 16 , wherein said interconnect layers are limited to dual patterning layers.
18 . The computer-readable storage medium as recited in claim 15 , wherein said deterministic boundary interconnect feature is configured to be connected to a power rail of an integrated circuit.
19 . The computer-readable storage medium as recited in claim 15 , wherein said deterministic boundary interconnect feature is configured to be used in a capacitor.
20 . The computer-readable storage medium as recited in claim 15 , wherein said deterministic boundary interconnect feature is one of a side-cell deterministic boundary interconnect feature and a U-shaped deterministic boundary interconnect feature and corresponds to one of an I/O buffer cell and an I/O support cell.
21 . The computer-readable storage medium as recited in claim 15 , wherein said deterministic boundary interconnect feature is a full-ring deterministic boundary interconnect feature and corresponds to a core block cell.