IP Library Granted Patent US 9,214,524
Granted Patent B2
US 9,214,524 · App. 13/586,091 · Granted Dec 15, 2015

Method of manufacturing a semiconductor device

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Quick Facts
Patent No.
US 9,214,524
App. No.
13/586,091
Granted
Dec 15, 2015
Kind
B2
Abstract

A semiconductor device includes a semiconductor substrate, a gate insulating film formed over the semiconductor substrate, a gate electrode formed on the gate insulating film, a first semiconductor layer which is embedded into a portion on both sides of the gate electrode in the semiconductor substrate, and which includes Si and a 4B group element other than Si, and a second semiconductor layer which is embedded into the portion on both sides of the gate electrode in the semiconductor substrate, so as to be superposed on the first semiconductor layer, and which includes Si and a 4B group element other than Si, wherein the gate electrode is more separated from an end of the first semiconductor layer than from an end of the second semiconductor layer.

Claims (29)

1. A method of manufacturing a semiconductor device, the method comprising:

forming a gate insulating film over a semiconductor substrate, and a gate electrode on the gate insulating film;

forming a first side wall on a side surface of the gate electrode;

forming a first recessed portion in the semiconductor substrate by using the gate electrode and the first side wall as a mask;

forming a second side wall on the first side wall;

forming a second recessed portion in the semiconductor substrate by using the gate electrode and the second side wall as a mask;

subsequently forming a first semiconductor layer in the second recessed portion;

after forming the first semiconductor layer, removing the second side wall;

after removing the second side wall, forming a second semiconductor layer in the first recessed portion;

wherein the first semiconductor layer and the second semiconductor layer comprise Si and a 4B group element other than Si, and

wherein a mole fraction of the 4B group element other than Si in the second semiconductor layer is higher than a mole fraction of the 4B group element other than Si in the first semiconductor layer.

2. The method according to claim 1 ,

wherein the 4B group element other than Si in the first semiconductor layer and the 4B group element other than Si in the second semiconductor layer are Ge or C.

3. The method according to claim 1 , further comprising:

forming, after forming the first semiconductor layer, a third semiconductor layer on the first semiconductor layer before forming the second semiconductor layer.

4. The method according to claim 3 ,

wherein the third semiconductor layer comprises Si or comprises Si and a 4B group element other than Si, and

wherein a mole fraction of the 4B group element other than Si in the third semiconductor layer is lower than the mole fraction of the 4B group element other than Si in the first semiconductor layer.

5. The method according to claim 4 , wherein the 4B group element other than Si in the second semiconductor layer is Ge or C.

6. The method according to claim 3 , further comprising:

forming, after forming of the second semiconductor layer, a fourth semiconductor layer on the second semiconductor layer.

7. The method according to claim 6 ,

wherein the fourth semiconductor layer comprises Si or comprises Si and a 4B group element other than Si, and

wherein a composition ratio of the 4B group element other than Si in the fourth semiconductor layer is lower than a composition of the 4B group element other than Si in the first semiconductor layer.

8. The method according to claim 7 ,

wherein the 4B group element other than Si in the second semiconductor layer is Ge or C.

9. The method according to claim 1 ,

wherein the mole fraction of the 4B group element other than Si in the second semiconductor layer is 0.20<x≦0.30 and the mole fraction of the 4B group element other than Si in the first semiconductor layer is 0.15≦x≦0.20, and

wherein the 4B group element other than Si in the first semiconductor layer and the 4B group element other than Si in the second semiconductor layer are Ge.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
MERGER Recorded May 24, 2023
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU LIMITED
Reel/Frame 064221/0545 →
CHANGE OF NAME AND CHANGE OF ADDRESS Recorded Jul 16, 2020
From: AIZU FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053481/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: AIZU FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053209/0468 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
CHANGE OF NAME Recorded Aug 30, 2012
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 028885/0172 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2012
From: TAMURA, NAOYOSHI, MR.
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 028805/0164 →